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參數(shù)資料
| 型號： | CY2081SL |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 6/6頁 |
| 文件大?。?/td> | 73K |
| 代理商： | CY2081SL |
CY2081A
6
Notes:
If pin 8 is OE, PD or SUSPEND, fill in only one value for
CLKA
Buffered reference clock is available on all outputs.
CLKA, CLKB and CLKC
, outputs can range from 500 kHz to
100 MHz (80 MHz at 3.3V)
CY2081A CONFIGURATION REQUEST FORM
1. OPERATING VOLTAGE(circle one)
2. INPUT REFERENCE FREQUENCY (Circleone)
3.3V
5.0V
Default reference = 14.318 MHz. If a different reference is desired,
specifythe frequency in the box to the right (must be between
10 MHz and 25 MHz for crystal, 1 MHz and 30 MHz for external clock):
4. OUTPUT CONFIGURATION
Fill in the desired frequencies, specifying kHz or MHz, for each output. Please adhere to the notes at the right. Contact
your local Cypress representative for assistance. After configuration, please fax the form to your local Cypress
representative.
CLKB
CLKC
Crystal
External Clock
5. FOR CYPRESS USE ONLY
Customer
Phone#
Engineer
Fax#
FAE/Sales
Date
3. OUTPUT CONTROL PIN (PIN 8) CONFIGURATION (Circleone)
CLKA (FS=0)
CLKA (FS=1)
OE (Default)
PD
FS
SUSPEND
If the Suspend option is desired, please circle what outputs must be suspended
CLKA
CLKB
CLKC
Customer Configuration
Marking
Date
Quantity
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2081WAF | MISCELLANEOUS CLOCK GENERATOR|DIE |
| CY26049-1 | Clocks and Buffers |
| CY26049-3 | Clocks and Buffers |
| CY26049-36 | Clocks and Buffers |
| CY26049-5 | Clocks and Buffers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2081SL112T | 制造商:CYPRESS 功能描述:* |
| CY2081SL-207 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY2081SL-239 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY2081SL-552 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY2081SL-552T | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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