參數(shù)資料
型號(hào): CY2040WAF
英文描述: Clocks and Buffers
中文描述: 時(shí)鐘和緩沖器
文件頁(yè)數(shù): 2/10頁(yè)
文件大小: 94K
代理商: CY2040WAF
CY2040WAF
PRELIMINARY
Document #: 38-07234 Rev. *A
Page 2 of 10
PAD
1
2
3
I/O
Vpp
OE1
PDOE2
Description
Vpp for programming, NC when in normal operating mode, Pad 1 and 8 are shorted on die
Out2 Control Pin - Out2 is disabled (HiZ) when LOW
EPROM Programmable Powerdown OR Output enable Pin - Out3 is disabled (HiZ) when
LOW (OE function). Part is powered down when LOW (PD function)
Battery supply or backup power source (2.5V to 3.6V)
Main VDD (2.7V
5.5V) (Vbatt has to be present when main Vdd is present)
32.768-kHz Xtal Pin
32.768-kHz Xtal Out Pin
Vpp for programming, NC when in normal operating mode. Pins 1 and 8 are shorted on die
No Connect
No Connect
Ground
10
30 MHz Xtal Pin
10
30 MHz Xtal Out Pin
32-kHz output
Three-state input when used for programming
32-kHz output OR 1 MHz
66 MHz output from PLL post divider
10
30 MHz Xtal output OR 5
15 MHz Xtal output (with divide-by-2 option) OR PLL post
divider output (1 MHz
66 MHz). Output programmable by user
Ground (Pad 17 and 18 have to be bonded out to one pin)
4
5
6
7
8
9
10
11
12
13
14
Vbatt
Vdd
Xg1
Xd1
Vpp
NC
NC
Vss
Xg2
Xd2
Out1
Programming
Out2
Out3
15
16
17,18
Vss
CY2040WAF
PAD Configurations
DIE SIZE w/Scribe
62.0 mils x 70.1mils
1574.8
μ
m x 1780.5
μ
m
# of Transistors
9517
DIE Substrate Attach:
GND
1 Vpp
2 OE1
3 PDOE2
4 Vbatt
5 Vdd
6 Xg1
7 Xd1
8 Vpp
11 Vss
13 Xd2
16 Out3
17 Vss
(double bond)
DIE Thickness 14 mils
14 Out1
15 Out2
12 Xg2
9 N/C
10 N/C
18
Vss
7C80400x (die says)
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