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參數(shù)資料
| 型號： | CY143 |
| 英文描述： | 2K x 16 Dual-Port Static RAM(193.25 k) |
| 中文描述： | 2K × 16雙口靜態(tài)存儲(chǔ)器（193.25十一） |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 193K |
| 代理商： | CY143 |
CY7C133
CY7C143
6
Switching Characteristics
Over the Operating Range
[6]
(continued)
Parameter
BUSY/INTERRUPT TIMING (For Master CY7C133)
Description
7C133-25
7C143-25
Min.
7C133-35
7C143-35
Min.
7C133-55
7C143-55
Min.
Unit
Max.
Max.
Max.
t
BLA
t
BHA
t
BLC
t
BHC
t
WDD
t
DDD
BUSY Low from Address Match
25
35
50
ns
BUSY High from Address Mismatch
20
30
40
ns
BUSY Low from CE LOW
20
25
35
ns
BUSY High from CE HIGH
Write Pulse to Data Delay
[12]
20
20
30
ns
50
60
80
ns
Write Data Valid to Read Data
Valid
[12]
BUSY High to Valid Data
[13]
Arbitration Priority Set Up Time
[14]
35
45
55
ns
t
BDD
t
PS
BUSY TIMING (For Slave CY7C143)
t
WB
t
WH
t
WDD
t
DDD
Write Data Valid to Read Data
Valid
[17]
Note 13
Note 13
Note 13
ns
5
5
5
ns
Write to BUSY
[15]
Write Hold After BUSY
[16]
Write Pulse to Data Delay
[17]
0
0
0
ns
20
25
30
ns
50
60
80
ns
35
45
55
ns
Switching Waveforms
Read Cycle No.1
[18, 19]
Notes:
12. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of
“
Read with BUSY, Master: CY7C133.
”
13. t
is a calculated parameter and is greater of 0,t
WDD
–
t
WP
(actual) or t
DDD
–
t
DW
(actual).
14. To ensure that the earlier of the two ports wins.
15. To ensure that write cycle is inhibited during contention.
16. To ensure that a write cycle is completed after contention.
17. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of
“
Read with Port-to-port Delay.
”
18. R/W is HIGH for read cycle.
19. Device is continuously selected, CE = V
IL
and OE = V
IL
.
t
RC
t
AA
t
OHA
DATA VALID
PREVIOUS DATA VALID
DATA OUT
ADDRESS
C133-5
Either Port Address Access
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY1461-000 | 制造商:TE Connectivity 功能描述:55PC0241-12-2/4/5/6CS2502 |
| CY14A | 功能描述:晶體 14.31818MHz Series 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負(fù)載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14AC | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負(fù)載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14ACS | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負(fù)載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
| CY14ACSMD | 功能描述:晶體 14.31818MHz 18pF 0C +70C RoHS:否 制造商:AVX 頻率:26 MHz 容差: 頻率穩(wěn)定性:50 PPM 負(fù)載電容:8 pF 端接類型:SMD/SMT 封裝 / 箱體:1210 (3225 metric) 工作溫度范圍:- 40 C to + 150 C 尺寸:2.5 mm W x 3.2 mm L x 0.85 mm H 封裝:Reel |
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