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參數(shù)資料
| 型號： | CXL5515M |
| 廠商： | Sony Corporation |
| 英文描述： | CMOS-CCD 1H Delay Line for PAL |
| 中文描述： | CMOS與CCD延遲線上半年為PAL制式 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 142K |
| 代理商： | CXL5515M |
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CXL5515M/P
E94904-ST
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5515M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL chroma signals
including the external lowpass filter.
Features
Single 5V power supply
Low power consumption
Built-in peripheral circuit
Built-in tripling PLL circuit
Center bias mode
Absolute Maximum Ratings
(Ta = 25°C)
Supply voltage
Operating temperature Topr
Storage temperature
Allowable power dissipation
V
DD
+6
V
–10 to +60
–55 to +150
°C
°C
Tstg
P
D
CXL5515M
CXL5515P
350
480
mW
mW
Recommended Operating Range
(Ta = 25C)
V
DD
5V ± 5%
Recommended Clock Conditions
(Ta = 25C)
Input clock amplitude
V
CLK
0.2 to 1.0Vp-p (0.4Vp-p Typ.)
Clock frequency
f
CLK
Input clock waveform
Sine wave
4.433619MHz
Block Diagram and Pin Configuration
(Top View)
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 575mVp-p (Max.)
Functions
848-bit CCD register
Clock driver
Auto bias circuit
Input center bias circuit
Sample and hold circuit
Tripling PLL circuit
Inverted output
Structure
CMOS-CCD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Auto-bias circuit
CCD
(848 bit)
Output circuit
(S/H 1 bit)
Bias circuit
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
5
6
7
8
V
DD
VCO OUT
VCO IN
CLK
2
3
4
1
IN
AB
OUT
V
SS
CXL5515M
8 pin SOP (Plastic)
CXL5515P
8 pin DIP (Plastic)
相關PDF資料 |
PDF描述 |
|---|---|
| CXL5515P | CMOS-CCD 1H Delay Line for PAL |
| CXL5520M | CMOS-CCD Baseband 1H Delay Line |
| CXL5520P | CMOS-CCD Baseband 1H Delay Line |
| CXP1021Q | System Controller for Compact Disc Players |
| CXP401 | SPC500 Series CPU core 6-KB ROM, 400-word RAM LCD controller/driver on chip |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CXL5515M/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-CCD 1H Delay Line for PAL |
| CXL5515P | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD 1H Delay Line for PAL |
| CXL5520M | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD Baseband 1H Delay Line |
| CXL5520M/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-CCD Baseband 1H Delay Line |
| CXL5520P | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD Baseband 1H Delay Line |
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