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參數(shù)資料
| 型號(hào)： | CXL5502M |
| 廠商： | Sony Corporation |
| 英文描述： | CMOS-CCD 1H Delay Line for NTSC |
| 中文描述： | CMOS與CCD延遲線上半年對(duì)NTSC |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大?。?/td> | 187K |
| 代理商： | CXL5502M |
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CMOS-CCD 1H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
The CXL5502M/N/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
The ICs contain a PLL circuit (quadruple progression).
Features
Single power supply (5V)
Low power consumption 95mW (Typ.)
Built-in peripheral circuits
Clamp level of I/O signal can be selected
Built-in quadruple PLL circuit
Functions
905-bit CCD register
Clock driver
Autobias circuit
Input clamp circuit
Sample and hold circuit
PLL circuit (quadruple progression)
Structure
CMOS-CCD
Absolute Maximum Ratings
(Ta = 25°C)
Supply voltage
Operating temperature Topr
Storage temperature
Allowable power dissipation
V
DD
6
V
–10 to +60
–55 to +150
°C
°C
Tstg
P
D
CXL5502M
CXL5502N
CXL5502P
400
260
800
mW
mW
mW
Recommended Operating Condition
(Ta = 25°C)
Supply voltage
V
DD
5 ± 5%
V
Recommended Clock Conditions
(Ta = 25°C)
Input clock amplitude
V
CLK
0.3 to 1.0
(0.5Vp-p typ.)
3.579545
Vp-p
Clock frequency
Input clock waveform
f
CLK
Sine wave
MHz
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
– 1 –
E89930E79-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL5502M/N/P
CXL5502M
14 pin SOP (Plastic)
CXL5502N
16 pin SSOP (Plastic)
CXL5502P
14 pin DIP (Plastic)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXL5502N | CMOS-CCD 1H Delay Line for NTSC |
| CXL5502P | CMOS-CCD 1H Delay Line for NTSC |
| CXL5504M | CMOS-CCD 1H Delay Line for NTSC |
| CXL5504P | CMOS-CCD 1H Delay Line for NTSC |
| CXM3000GA | GSM IC(GSM900/1800 Dual Band,RF Front End,PLL Module)(GSM制式芯片（GSM900/1800雙波段+RF前端+鎖相環(huán)模塊）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXL5502M/N/P | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:CMOS-CCD 1H Delay Line for NTSC |
| CXL5502N | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:CMOS-CCD 1H Delay Line for NTSC |
| CXL5502P | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:CMOS-CCD 1H Delay Line for NTSC |
| CXL5504M | 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:CMOS-CCD 1H Delay Line for NTSC |
| CXL5504M/P | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TV/Video Delay Line Circuit |
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