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參數(shù)資料
| 型號： | CXK79M72C160GB |
| 英文描述： | MEMORY-SigmaRAM 16Meg 1x1 HSTL I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
| 中文描述： | 內(nèi)存SigmaRAM 16Meg 1x1 HSTL的I / O（256 × 72）（27頁364K牧師7/6/01） |
| 文件頁數(shù)： | 9/30頁 |
| 文件大小： | 554K |
| 代理商： | CXK79M72C160GB |
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SONY
Σ
RAM CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.0
9 / 30
July 19, 2002
Burst (Continue) Operations
Burst operations follow the
Linear Burst
address sequence depicted in the table below:
Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four
(4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal ad-
dress wraps back to the initial external (base) address.
Depth Expansion
Depth expansion in these devices is supported via programmable chip enables E2 and E3. The active levels of E2 and E3 are
programmable through the static inputs EP2 and EP3 respectively. When EP2 is tied “high”, E2 functions as an active-high
input. When EP2 is tied “l(fā)ow”, E2 functions as an active-low input. Similarly, when EP3 is tied “high”, E3 functions as an
active-high input. And, when EP3 is tied “l(fā)ow”, E3 functions as an active-low input.
The programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By
programmingE2andE3offour devices ina binarysequence (00,01, 10,11),andbydrivingE2andE3withexternaladdress
signals, the four devices can be made to look like one larger device.
When these devices are deselected via chip enable E1, the output clocks continue to toggle. However, when these devices
are deselected via programmable chip enables E2 or E3, the output clocks are forced to a Hi-Z state. See the Clock Truth
Table for further information.
Output Driver Impedance Control
The impedance of the data and clock output drivers in these devices can be controlled via the static input ZQ. When an ex-
ternal impedance matching resistor (RQ) is connected between ZQ and V
SS
, output driver impedance is set to one-fifth the
value of the resistor, nominally. See the DC Electrical Characteristics section for further information.
Output driver impedance is updated whenever the data output drivers are in an inactive (High-Z) state. See the Clock Truth
Table section for information concerning which commands deactivate the data output drivers.
At power up, 8192 clock cycles followed by any command that deactivates the data output drivers are required to ensure that
the output impedance has reached the desired value.
Note
: The impedance of the output drivers will drift somewhat due to changes in temperature and voltage. Consequently,
during operation, the output drivers should be deactivated periodically in order to update the output impedance and ensure
that it remains within specified tolerances.
Power-Up Sequence
Forreliabilitypurposes,Sonyrecommendsthat powersuppliespowerupinthefollowingsequence:V
SS
,V
DD
,V
DDQ
,V
REF
,
and Inputs. V
DDQ
should never exceed V
DD
. If this power supply sequence cannot be met, a large bypass diode may be re-
quired between V
DD
and V
DDQ
. Please contact Sony Memory Application Department for further information.
A(1:0)
Sequence Key
1st (Base) Address
00
01
10
11
A1, A0
2nd Address
01
10
11
00
(A1 xor A0), A0
3rd Address
10
11
00
01
A1, A0
4th Address
11
00
01
10
(A1 xor A0), A0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXK79M72C161GB | MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
| CXK79M72C164GB | MEMORY-SigmaRAM 16Meg 1x1z HSTL I/O (256K x 72) (27 pages 368K Rev. 7/6/01) |
| CXK79M72C165GB | MEMORY-SigmaRAM 16Meg 1x1z LVCMOS I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
| CXO-M10 | Telecommunication IC |
| CXO-MS10 | Telecommunication IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK79M72C161GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (256K x 72) (27 pages 364K Rev. 7/6/01) |
| CXK79M72C164GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x1Dp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36) |
| CXK79M72C165GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36) |
| CXK79M72C165GB-4 | 制造商:SONY 功能描述: |
| CXK900L-S | 制造商:CHDS 功能描述:HEAT SINK 130x30x10mm |
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