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參數(shù)資料
| 型號： | CXD3609R |
| 英文描述： | Timing Generator for Progressive Scan CCD Image Sensor |
| 中文描述： | 時序發(fā)生器傳感器逐行掃描CCD圖像 |
| 文件頁數(shù)： | 3/72頁 |
| 文件大?。?/td> | 901K |
| 代理商： | CXD3609R |
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3
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CXD3609R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Symbol
I/O
—
I
I
O
O
I
—
O
—
O
—
O
O
—
O
—
—
O
O
O
O
O
O
—
O
I
Description
GND
Internal system reset input. High: Normal operation, Low: Reset control.
Normally apply reset during power-on.
Schmitt trigger input/protective diode on power supply side
Control input used to switch sync system. High: CKI sync, Low: MCKO sync.
With pull-down resistor
Vertical direction line identification pulse output/exposure time identification
pulse output.
Switching possible using the serial interface data. (Default: ID)
Memory write timing pulse output.
Internal SSG enable. High: Internal SSG valid, Low: External sync valid.
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
CCD reset gate pulse output.
Logic phase adjustment possible using the serial interface data.
GND
CCD horizontal register clock output.
Logic phase adjustment possible using the serial interface data.
5/3.3V power supply. (Power supply for H)
CCD horizontal register clock output.
Logic phase adjustment possible using the serial interface data.
CCD horizontal register clock output.
Logic phase adjustment possible using the serial interface data.
GND
CCD horizontal register clock output.
Logic phase adjustment possible using the serial interface data.
5/3.3V power supply. (Power supply for H)
3.3V power supply. (Power supply for CDS)
CCD precharge level sample-and-hold pulse output.
Logic phase adjustment possible using the serial interface data.
CCD data level sample-and-hold pulse output.
Logic phase adjustment possible using the serial interface data.
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD dummy signal clamp pulse output.
CCD optical black signal clamp pulse output.
The horizontal OB pattern can be changed using the serial interface data.
Clock output for analog/digital conversion IC.
Logic phase adjustment possible using the serial interface data.
GND
Inverter output.
Inverter input.
V
SS
1
RST
SNCSL
ID/EXP
WEN
SSGSL
V
DD
1
RG
V
SS
2
H1A
V
DD
2
H1B
H2A
V
SS
3
H2B
V
DD
3
V
DD
4
XSHP
XSHD
PBLK
CLPDM
OBCLP
ADCLK
V
SS
4
CKO
CKI
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相關(guān)代理商/技術(shù)參數(shù) |
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| CXD3611R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Progressive Scan CCD Image Sensor |
| CXD3615R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Frame Readout CCD Image Sensor |
| CXD3619R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for Frame Readout CCD Image Sensor |
| CXD3815Q | 制造商:Sony Semiconductor Solutions Division 功能描述:IC, VIDEO DECODER, QFP-208 |
| CXD4000R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fingerprint Verification System LSI |
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