
–
4
–
CXA3271AGE
Pin Description
Serial
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
19
18
17
16
15
24
23
22
21
20
28
27
26
25
2B
2C
2D
2E
2F
3B
3C
3D
3E
3F
4B
4C
4D
4E
4F
5B
5C
5D
5E
5F
6B
6C
6D
6E
6F
7B
7C
7D
7E
7F
SUB
AV
DD
AV
SS
TEST1
TEST2
MODE
DI0
DI1
DI2
XSP
HD
CLK
C_CLK
C_CK
ADCLK
DV
DD
DV
SS
DV
SS
CSRO
RSRO
VOS
VH
VM
VL
VCS_S
SUB
AV
DD
AV
SS
AOUT
VCS_O
Power
Power
Power
D/I
D/I
D/I
D/I
D/I
D/I
D/I
D/I
D/I
D/I
D/O
D/O
Power
Power
Power
D/O
D/O
A/O
A/O
A/O
A/O
A/O
Power
Power
Power
A/O
A/O
Substrate electrode (chip rear surface electrode) 3.3V.
Analog power supply 3.3V.
Analog GND.
Test mode selection. Connect to GND.
Test mode selection. Connect to GND.
Connect to GND.
Gain setting input. (LSB)
Gain setting input.
Gain setting input. (MSB)
Sense start pulse input (negative pulse).
The column and row shift registers and the timing generator are
cleared by this signal.
Connect to GND.
Main clock. (1 to 2MHz)
Column shift register clock.
Connect to C_CK (4E).
Column shift register clock output.
Connect to C_CLK (4D).
Outputs the internally delayed input clock.
Digital power supply 3.3V.
Digital GND.
Digital GND.
Column shift register final output. (Connection is not required.)
Row shift register final output. (Connection is not required.)
Output amplifier reference voltage monitor. (1.65V)
Sensor charge voltage monitor. (1 LSB = 80mV)
Adjustable within the range of 1.92 to 2.48V by the three bits
DI[0:2].
Sense amplifier reference voltage monitor. (1.85V)
Dummy cell charge voltage monitor for canceling parasitic
capacitance.
VL = 2VM
–
VH
Sense amplifier current source bias monitor.
(Do not connect.)
Substrate electrode (chip rear surface electrode) 3.3V.
Analog power supply 3.3V.
Analog GND.
Sensor output.
Output amplifier and output buffer current source bias monitor.
(Do not connect.)
Land No.
Symbol
I/O
Description