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Diversity Receiver Front End
CX42053
101431B
March 12, 2002
Skyworks
9
Proprietary Information and Specifications Are Subject to Change
Evaluation Board Description
The CX42053 Evaluation Board is used to test the CX42053
mxer and LNA performance. The CX42053 Evaluation Board
schematic diagramis shown in Figure 10. Table 6 contains I/O
matching network components used in the schematic. The
schematic shows the basic design of the Evaluation Board for
the RF range of 800 to 1000 MHz. The IF matching circuitry has
been optimzed for 60 to 130 MHz. Figure 11 displays the
Evaluation Board layout.
Circuit Design Configurations ________________________
The following design considerations are general in nature and
must be followed regardless of final use or configuration:
1. Paths to ground should be made as short as possible.
2. The downset paddle of the PQFP provides necessary
electrical grounding and is the main thermal conduit for
heat dissipation. Any printed circuit board using the
CX42053 must have sufficient solder mask clearance
beneath the IC (i.e., approximately 110 percent of the
downset paddle). This provides adequate solder coverage
for the downset paddle and mnimzes excessive lead
standoff. Multiple vias to the grounding layer beneath the
device are required for maximumthermal relief.
3. The inclusion of external bypass capacitors on the VSS
and VDD voltage inputs of the LNAs and mxers is
recommended. The application schematic in Figure 10
shows these capacitors (1000 pF and 12 pF) in shunt with
each control switch, as well as the VSS supply. The
1000 pF capacitor serves as a low frequency bypass, while
the 12 pF capacitor prevents any RF signals fromcoupling
on to the DC supply voltages. It is recommended that the
bypass capacitors be placed as close as possible to the
CX42053 for best results.
4. The LNA receives its bias voltage via the LNA output pin.
The use of a blocking capacitor (RF short) on the LNA
input/output and mxer input is required.
5. Ceramc or wire-wound balanced transformers (baluns)
may be used to provide the differential input to the active
mxer. The secondary center tap of these baluns provides
the DC return path for the mxer bias current. Balun
selection criterion should include DC current handling
capability, differential phase/amplitude balance, insertion
loss, and temperature performance.
6. The application of an image-reject filter between the LNA
and mxer is recommended.
7. For proper switching of the control interface circuits, the
following conditions must be met:
OFF: 0 VDC
≤
V
IN
≤
0.5 VDC @ 30
μ
A
ON: 3.0 VDC
≤
V
IN
≤
VDD @ 120
μ
A
LNA Testing Procedure_______________________________
Use the following procedure to set up the CX42053 Evaluation
Board for LNA testing. Refer to Figure 12 for guidance:
1. Set all the DIP switches to OFF. For information on the
switch settings, refer to Table 7.
2. Connect the CX42053 Evaluation Board to
±
5 VDC power
supplies using insulated supply cables. VDD should be set
to +5.0 V and VSS to –5.0 V. If available, enable the
current limting function of the power supplies as follows:
+ 5 VDC supply current limt = 200 mA
–5 VDC supply current limt = 50 mA
Connect red and yellow banana plugs to VDD, a purple
plug to VSS, and a black plug to ground. Connect a three-
slot plug to the side (JP1) and a two-slot plug to the top
(JP2).
3. Connect a signal generator to the LNA A input port (J1).
Set the generator to the desired RF frequency at a power
level of –20 dBm but do not enable.
4. Connect a spectrumanalyzer to the output port of LNA A
(J2).
5. Enable the power supply by turning switches #2 and #4
ON.
6. Enable the RF signal and take measurements.
7. Repeat steps 3 through 6 for LNA B, but use switches #4
and #5 to enable the power supply.
Mxer Testing Procedure______________________________
Use the following procedure to set up the CX42053 Evaluation
Board for mxer testing. Refer to Figure 13 for guidance:
1. Set all the DIP switches to OFF. For information on the
switch settings, refer to Table 7.
2. Connect the CX42053 Evaluation Board to
±
5 VDC power
supplies using insulated supply cables. VDD should be set
to +5.0 V and VSS to –5.0 V. If available, enable the
current limting function of the power supplies as follows:
+ 5 VDC supply current limt = 200 mA
–5 VDC supply current limt = 50 mA
Connect red and yellow banana plugs to VDD, a purple
plug to VSS, and a black plug to ground. Connect a three-
slot plug to the side (JP1) and a two-slot plug to the top
(JP2).
3. Connect a signal generator to the LO1 input port (J9). Set
the generator to the desired LO frequency at a power level
of 0 dBm but do not enable.