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參數(shù)資料
| 型號： | CW000504 |
| 英文描述： | CW000504 GigaBlaze transceiver cores G12 .18 micron |
| 中文描述： | CW000504 GigaBlaze收發(fā)器對應原館內G12核心的0.18微米 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 123K |
| 代理商： | CW000504 |
Figure 1. GigaBlaze Block Diagram
GigaBlaze Block Diagram
GigaBlaze technology provides a point-to-point, full-duplex, differential, serial
communications link that transfers data at up to 2.5 Gbits/sec. It is a protocol-
independent serial interface with a direct interface option to optics, twinax line
or a PCB trace. Clock recovery and synchronization are included. As illustrated
in Figure 1 above, this CMOS implementation is ideal for applications con-
strained by power and size, and offers a competitive solution to the GaAs and
BiCMOS standard parts available today.
High-Speed Protocols
GigaBlaze technology provides a physical layer for emerging standard, high-speed
communications protocols, such as Fibre Channel, Gigabit Ethernet, and the
emerging System Area Network (SAN) as well as proprietary board-to-board or
box-to-box serial communications.
GigaBlaze Transceiver Cores
Features
A gigabit high-speed serial interface CMOS
core;can be integrated with other industry-
standard cores and user-defined logic for a
system-on-a-chip solution
Supports serial transfer rates of up to
2.5 Gbits/sec
Multiple cores can be integrated on a
single ASIC
Supports full duplex operation
Self testability via serial loop back mode
Available in LSI Logic’s leading-edge,
CMOS technologies
Core behavioral models with timing
information and simulation verification
environment models available with complete
test vector sets
Complete evaluation platforms available
Worldwide design resource center support
TX Clock Generator
Serializer
Transmit
Buffer
Data/Clock
Recovery
RX Clock Generator
Receive
Buffer
RXDATA
BIST
RBC
clock
TXP
TXN
RXP
RXN
Receiver
REFCLK
or TBC
TXDATA
Transmitter
Transceiver
Deserializer
and Data
Alignment
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