
Aeroflex Circuit Technology
28
SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700
MEMWR
MEM/REG
A15-A00
IOEN
SELECT
STRBD
(Internal)
16MHz Clock
RD/WR
READYD
See Note 1
td1
tpw1
D15-D00
td2
RAM ADDRESS VALID
td3
RAM DATA VALID
MEMENA-OUT
tpw2
Figure 31 – CPU Writes to RAM Timing
CPU Writes to Ram
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
150
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
tpw1
READYD pulse width (CPU Handshake)
50
-
ns
td3
CPU MEMWR low delay
-
120
ns
tpw2
CPU MEMWR low pulse width
70
-
ns
tr
READYD to STRBD release
-
1.37
μs
tz
(SELECT
STRBD) to IOEN
-
1.8
μs
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5μs of IOEN going active. READYD will go away within one clock cycle maximum.
See Note 2
tz
tr