
CLOCK
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CS9/CSP SERIES:  CLOCK OSCILLATOR, PECL, +3.3 VDC or +2.5VDC 
RALTRON ELECTRONICS CORP. 
!
 10651 N.W. 19
t h
 St 
!
 Miami, Florida 33172 
!
 U.S.A. 
phone: (305) 593-6033 
!
 fax: (305) 594-3973 
!
 e-mail: sales@raltron.com 
!
 WEB: http://www.raltron.com 
DESCRIPTION:  A crystal controlled, high frequency, highly stable oscillator, adhering to Positive Emitter 
Coupled Logic (PECL) Standards.  The output can be Tri-stated to facilitate testing or combined multiple clocks.  
The device is contained in a sub-miniature, very low profile, leadless ceramic SMD package with 6 gold contact 
pads.  This miniature oscillator is ideal for today's automated assembly environments.
 APPLICATIONS AND FEATURES: 
" 
Infiniband; 10GbE; Network Processors; SOHO Routing; Switches; WAN Interfaces 
" 
Common Frequencies:  106.25 MHz; 125 MHz; 150 MHz; 155.52 MHz; 156.25 MHz; 161.1328 MHz 
" 
+3.3 VDC or +2.5VDC PECL 
" 
Frequency Range from 50.000 to 315 MHz 
" 
No multiplication 
" 
Miniature Ceramic SMD Package Available on Tape and Reel 
" 
Lead Free and ROHS Compliant 
$ 
ABSOLUTE MAXIMUM RATINGS: 
PARAMETER 
SYMBOL 
VALUE 
UNIT 
Operating temperature range Ta 
-40…+85 
°
C 
°
C 
VDC 
Storage temperature range 
T(stg) 
-55…+90 
Supply voltage  
Vcc 
-0.5…+5.0 
Maximum Input Voltage 
Vi 
Vss-0.5…Vcc+0.5 
VDC 
Maximum Output Voltage 
$ 
ELECTRICAL PARAMETERS: 
Vo 
 Vss-0.5…Vcc+0.5 
VDC 
PARAMETER 
SYMBO
L 
fo 
Vcc 
Is 
Voh 
Vol 
DC 
tr / tf 
TEST CONDITIONS
*1
VALUE 
UNIT 
Nominal Frequency 
Supply Voltage 
Supply Current 
Output Logic Type 
Load 
Connected between each output and Vcc – 2.0 VDC 
min 
max 
Measured at 50% of Vcc 
Measured at 20/80% and 80/20% Vcc Levels 
Integrated Phase tji RMS, Fj = 12 kHz…20 MHz 
Integrated Phase RMS tii offset frequency 50KHz to 
80MHz  
Deterministic period Jitter tdj  using  wavecrest analyz.   0.0TYP **  
Random period Jitter trj  using  wavecrest analyz.           2.5 TYP **  
Peak to Peak Jitter Tp-p  using wavecrest analyz.         25 TYP**  
f=
10 Hz  
f=
1 KHz 
f=
10 KHz 
f=
 >/=100 KHz 
Op. Temp., Aging, Load, Supply and Cal. Variations 
High Voltage or No Connect 
Ground   
50.000 ~ 315.00** 
+3.3 or +2.5 
±
5% 
80.0 MAX  
PECL 
50 
Vcc-1.025 
Vcc-1.620 
40/60 to 60/40 or 45/55 to 55/45
0.5 TYP 
*2
0.3 TYP** 
MHz 
VDC 
mA 
VDC 
VDC 
% 
ns 
ps 
Output Voltage Levels 
Duty Cycle 
Rise / Fall Time 
0.5 TYP** 
ps 
ps 
ps 
ps 
Jitter  
J 
Phase Noise typ. 
@155.52MHz 
£(
f) 
£(
f) 
£(
f) 
£(
f) 
f/fc 
En 
Dis 
  -65  
-120   
-140 
-145 
±
20, 
±
25, 
±
50, or 
±
100 MAX
*3
0.7
Vcc MIN 
0.3
Vcc MAX 
dBc/Hz 
dBc/Hz 
dBc/Hz 
dBc/Hz
Ppm 
VDC 
VDC 
Overall Frequency Stability 
Pin 1      Output Enabled  
              Output Disabled   
*1 Test Conditions Unless Stated Otherwise:  Nominal Vcc, Nominal Load, +25 
±
3
°
C 
*2 Frequency Dependent
*3 Not All Stabilities Available With All Temperature Ranges—Please Consult Factory For Availability