6.18 Self Status Register - Address 19h 15 14 13 12 11 10 9 8 Link OK Po" />
參數(shù)資料
型號： CS8952-IQZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 54/81頁
文件大?。?/td> 0K
描述： IC TXRX 100/10 PHY 100TQFP
標準包裝： 90
類型： 收發(fā)器
規(guī)程： MII
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 759 (CN2011-ZH PDF)
其它名稱： 598-1208
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
58
DS206F1
6.18
Self Status Register - Address 19h
15
14
13
12
11
10
9
8
Link OK
Power
Down
Receiving
Data
Descrambler
Lock
Disable CRS
on Time-out
Auto-Neg
Enable Status
PAUSE
FEFI Enable
7
654
32
10
Full Duplex
10BASE-T
Mode
CIM Status
PHY Address
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Link OK
Read Only
0
When set, this bit indicates that a valid link connec-
tion has been detected. The type of link established
may be determined from bits 6, 7, and 9. When clear,
this bit indicates that a valid link connection does not
exist. This bit may be used to determine the current
status of the link.
14
Power Down
Read Only
1
When high, this bit indicates that the CS8952 is in a
low power state.
13
Receiving Data
Read Only
0
This bit is high whenever the CS8952 is receiving
valid data. It is a direct copy of the state of the
RX_DV pin accessible by software.
12
Descrambler Lock
Read Only
0
When high, this bit indicates that the descrambler
has successfully locked to the scrambler seed of the
far-end transmitter and is able to descramble
received data.
11
Disable CRS on
Time-out
Read/Write Reset to the logic
inverse of the
value on the
REPEATER pin.
This bit controls the state of the CRS pin upon a
descrambler time-out. When set, CRS will be forced
low upon a descrambler time-out, and will not be
released until the descrambler has re-acquired syn-
chronization.
10
Auto-Neg Enable
Status
Read Only
If auto-negotiation
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0.
This bit reflects the value of bit 12 in the Basic Mode
Control Register (address 00h). When set, it indi-
cates that auto-negotiation has been enabled. When
clear, this bit indicates that the mode of the CS8952
has been forced to that indicated by bits 6, and 7.
9
PAUSE
Read Only
0
When set, this bit indicates that the Flow-Control
PAUSE function has been negotiated. This indicates
that both the local device and the link partner have
advertised this capability.
8
FEFI Enable
Read/Write 0
This bit controls the Far-End Fault Generate and
Detect state machines. When this bit is set and auto-
negotiation is disabled (bit 10 is clear), both state
machines are enabled. When clear, this bit disables
both state machines.
7
Full Duplex
Read Only
If a full duplex
mode is enabled
via the AN[1:0]
pins, reset to 1;
otherwise, reset to
0.
When set, this bit indicates that the CS8952 has
been configured for Full-Duplex operation.
6
10BASE-T Mode
Read Only
0
When set, this bit indicates that the CS8952 has
been configured for 10 Mb/s operation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8952-IQZR 功能描述:以太網(wǎng) IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
CS8952T 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-CQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER
CS8952T-IQR 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel
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