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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CS8421-CNZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/17闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC SAMPLE RATE CONVERTER 20QFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 60 |
| 椤炲瀷锛� | 閲囨ǎ鐜囪綁(zhu菐n)鎻涘櫒 |
| 鎳�(y墨ng)鐢細 | 鏁�(sh霉)瀛楅煶闋� |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-QFN |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-QFN 瑁搁湶鐒婄洡锛�5x5锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 759 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 598-1018-ND - BOARD EVAL FOR CS8421 |
| 鍏跺畠鍚嶇ū锛� | 598-1730 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�鐣�(d膩ng)鍓嶇5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�
DS641F6
13
CS8421
6.
After powering up the CS8421,
RST should be held low until the power supplies and clocks are settled.
7.
The maximum possible sample rate is XTI/128.
8.
OLRCK must remain high for at least 8 OSCLK periods in TDM Mode.
9.
Only the input or the output serial port can be set as master at a given time.
Master Mode (Note 9)
I/OSCLK Frequency (non-TDM)
64*Fsi/o
MHz
OSCLK Frequency (TDM)
256*Fso
MHz
I/OLRCK Duty Cycle
45
55
%
I/OSCLK Duty Cycle
45
55
%
I/OSCLK Falling Edge to I/OLRCK Edge
tlcks
-5
ns
OSCLK Falling Edge to OLRCK Edge (TDM)
tfss
-5
ns
OSCLK Falling Edge to SDOUT Output Valid
tdpd
-7
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
3-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
5-
ns
Parameters
Symbol
Min
Max
Units
t
ds
OLRCK
(input)
t
dh
t
sckh
t
sckl
t
fsh
t
fss
OSCLK
(input)
TDM_IN
(input)
SDOUT
(output)
MSB
t
dpd
MSB-1
MSB
MSB-1
t
lrckh
t
ds
MSB
t
dh
t
dpd
MSB-1
I/OLRCK
(input)
I/OSCLK
(input)
SDIN
(input)
SDOUT
(output)
MSB
MSB-1
t
sckh
t
sckl
t
lcks
t
lckd
Figure 1. Non-TDM Slave Mode Timing
Figure 2. TDM Slave Mode Timing
t
ds
OLRCK
(output)
t
dh
t
dpd
t
fss
OSCLK
(output)
TDM_IN
(input)
SDOUT
(output)
MSB
MSB-1
MSB
MSB-1
t
ds
MSB
t
dh
t
dpd
MSB-1
t
lcks
I/OLRCK
(output)
I/OSCLK
(output)
SDIN
(input)
SDOUT
(output)
MSB
MSB-1
Figure 3. Non-TDM Master Mode Timing
Figure 4. TDM Master Mode Timing
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| CS8421-CNZR | 鍔熻兘鎻忚堪:闊抽牷 DSP IC 32-Bit 192kHz Asynchron Stereo SRC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 宸ヤ綔闆绘簮闆诲: 闆绘簮闆绘祦: 宸ヤ綔婧害鑼冨湇: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: 灏佽:Tube |
| CS8421-CZZ | 鍔熻兘鎻忚堪:闊抽牷 DSP 32-Bit 192kHz Async Stereo SRC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 宸ヤ綔闆绘簮闆诲: 闆绘簮闆绘祦: 宸ヤ綔婧害鑼冨湇: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: 灏佽:Tube |
| CS8421-CZZR | 鍔熻兘鎻忚堪:闊抽牷 DSP IC 32-Bit 192kHz Asynchron Stereo SRC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 宸ヤ綔闆绘簮闆诲: 闆绘簮闆绘祦: 宸ヤ綔婧害鑼冨湇: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: 灏佽:Tube |
| CS8421-DZZ | 鍔熻兘鎻忚堪:闊抽牷 DSP 32-Bit 192kHz Async Stereo SRC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 宸ヤ綔闆绘簮闆诲: 闆绘簮闆绘祦: 宸ヤ綔婧害鑼冨湇: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: 灏佽:Tube |
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