![](http://datasheet.mmic.net.cn/Cirrus-Logic-Inc/CS8406-DZZ_datasheet_104571/CS8406-DZZ_7.png)
DS580F6
7
CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Notes:
9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is dic-
tated by the timing requirements necessary to access the Channel Status and User Bit buffer memory.
Access to the control register file can be carried out at the full 6 MHz rate.
10. Tsch must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For fsck < 1 MHz.
Parameter
Symbol
Min
Typ
Max
Units
CCLK Clock Frequency
fsck
0-
6.0
MHz
CS High Time Between Transmissions
tcsh
1.0
-
s
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
MAX ((1/256 FS + 8), 66)
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
tdh
15
-
ns
CCLK Falling to CDOUT Stable
tpd
--
50
ns
Rise Time of CDOUT
tr1
--
25
ns
Fall Time of CDOUT
tf1
--
25
ns
Rise Time of CCLK and CDIN
tr2
--
100
ns
Fall Time of CCLK and CDIN
tf2
--
100
ns
t r2
t f2
t dsu
t dh
t sch
t scl
CS
CCLK
CDIN
t css
t pd
CDOUT
tcsh
Figure 3. SPI Mode Timing