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參數(shù)資料
| 型號(hào)： | CS8311YDR8 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
| 中文描述： | 三端固定電壓調(diào)節(jié)器 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 73K |
| 代理商： | CS8311YDR8 |
CS8311
http://onsemi.com
4
CIRCUIT DESCRIPTION
VOLTAGE REFERENCE AND OUTPUT CIRCUITRY
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (Figure 2).
Figure 2. Typical Circuit Waveforms for Output
Stage Protection
I
OUT
Load
Dump
V
IN
V
OUT
Current
Limit
Short
Circuit
> 30 V
If the input voltage rises above 30 V (e.g. load dump), the
output shuts down. This response protects the internal
circuitry and enables the IC to survive unexpected voltage
transients.
Should the junction temperature of the power device
exceed 180
°
C (typ) the load current capability is reduced
thereby preventing thermal overload. This thermal
management function is an effective means to prevent die
overheating since the load current is the principle heat
source in the IC.
REGULATOR CONTROL FUNCTIONS
The CS8311 contains two microprocessor compatible
control functions: ENABLE and RESET (Figure 3).
Figure 3. Circuit Waveform
(1) = No Reset Delay Capacitor
(2) = With Reset Delay Capacitor
V
IN
V
OUT
ENABLE
RESET
VR
LO
VR
PEAK
VR
PEAK
For 11 V < V
IN
< 26 V
V
IN(H)
V
RH
ON
V
RL
OFF
(1)
(2)
ENABLE Function
The ENABLE function switches the output transistor ON
and OFF. When the voltage on the ENABLE lead exceeds
1.4 V typ, the output pass transistor turns off, leaving a high
impedance facing the load. The IC will remain in Sleep
mode, drawing only 50
μ
A (max), until the voltage on this
input drops below the ENABLE threshold.
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until V
OUT
is within 1.0 V of the regulated output
voltage, or when V
OUT
drops out of regulation, and is lower
than 1.1 V below the regulated output voltage. A hysteresis
of 50 mV is included in the function to minimize
oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for V
OUT
as low
as 1.0 V.
Figure 4. RC Network for RESET Delay
V
OUT
CS8311
5.0 V to
μ
P
and System
Power
RESET
R
RST
to
μ
P
RESET
Port
C
RST
C
OUT
An external RC network on the lead (Figure 4) provides
a sufficiently long delay for most microprocessor based
applications. RC values can be chosen using the following
formula:
RTOTCRST
–tDelay
VT
VRST
ln
VOUT
VOUT
where:
R
RST
= RESET Delay resistor
R
IN
=
μ
P port impedance
R
TOT
= R
RST
in parallel with R
IN
C
RST
= RESET Delay capacitor
t
Delay
= desired delay time
V
RST
= V
SAT
of RESET lead (0.7 V @ turn – ON)
V
T
= RESET threshold.
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