參數(shù)資料
型號(hào): CS8147
廠商: ZF Electronics Corporation
英文描述: 10V/5V Low Dropout Dual Regulator with ENABLE
中文描述: 10V/5V低壓差穩(wěn)壓雙用ENABLE
文件頁(yè)數(shù): 6/8頁(yè)
文件大小: 173K
代理商: CS8147
6
C
Since both outputs are controlled by the same
the CS8147 is ideal for applications where a sleep mode is
required. Using the CS8147, a section of circuitry such as a
display and nonessential 5V circuits can be shut down
under microprocessor control to conserve energy.
The test applications circuit diagram shows an automotive
radio application where the display is powered by 10V
from V
OUT1
and the Tuner IC is powered by 5V from
V
OUT2
. Neither output is required unless both the ignition
and the Radio On/OFF switch are on.
,
The secondary output V
OUT2
is inherently stable and does
not require a compensation capacitor. However a compen-
sation capacitor connected between V
OUT1
and ground is
required for stability in most applications.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start-up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instabili-
ty. The aluminum electrolytic capacitor is the least expen-
sive solution, but, if the circuit operates at low tempera-
tures (-25C to -40C), both the value and ESR of the capac-
itor will vary considerably. The capacitor manufacturers
data sheet usually provides this information.
The value for the output capacitor C2 shown in the test
and applications circuit should work for most applications,
however it is not necessarily the optimized solution.
To determine acceptable value for C2 for a particular
application, start with a tantalum capacitor of the recom-
mended value and work towards a less expensive alterna-
tive part.
Step 1:
Place the completed circuit with a tantalum capaci-
tor of the recommended value in an environmental cham-
ber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2:
With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscil-
lations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
Step 3:
Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4:
Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage condi-
tions.
Step 5:
If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger stan-
dard capacitor value.
Step 6:
Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7:
Raise the temperature to the highest specified oper-
ating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found for each output, a safety factor should be
added to allow for the tolerance of the capacitor and any
variations in regulator performance. Most good quality
aluminum electrolytic capacitors have a tolerance of ±20%
so the minimum value found should be increased by at
least 50% to allow for this tolerance plus the variation
which will occur at low temperatures. The ESR of the
capacitors should be less than 50% of the maximum allow-
able ESR found in step 3 above.
The maximum power dissipation for a dual output regula-
tor (Figure 1) is
P
D(max)
= {V
IN(max)
D V
OUT1(min)
}I
OUT1(max)
+
{V
IN(max)
D V
OUT2(min)
}I
OUT2(max)
+ V
IN(max)
IQ (1)
Where:
V
IN(max)
is the maximum input voltage,
V
OUT1(min)
is the minimum output voltage from V
OUT1
,
V
OUT2(min)
is the minimum output voltage from V
OUT2
,
I
OUT1(max)
is the maximum output current, for the appli-
cation,
I
OUT2(max)
is the maximum output current, for the appli-
cation, and
I
Q
is the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum permissi-
ble value of R
Q
JA
can be calculated:
R
Q
JA
=
(2)
The value of R
JA
can then be compared with those in
the package section of the data sheet. Those packages with
R
JA
's less than the calculated value in equation 2 will keep
the die temperature below 150C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
150C - T
A
P
D
ENABLE
Applications
Stability Considerations
Calculating Power Dissipation
in a Dual Output Linear Regulator
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