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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | CS8130-CS |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 3/28闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC IR TRANSCEIVER 2-5V 20-SSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 66 |
| 椤�(l猫i)鍨嬶細 | 鏀剁櫦(f膩)鍣� |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-SSOP |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 758 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 598-1161-ND - BOARD EVAL FOR CS8130 |
| 鍏跺畠鍚嶇ū(ch膿ng)锛� | 598-1203-5 |
绗�1闋�(y猫)绗�2闋�(y猫)鐣�(d膩ng)鍓嶇3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)
then switch to "programmed T period" mode to
reduce processing overhead in the host CPU.
Clock Generation
The primary clock required is 3.6864 MHz. This
may be generated by attaching a 3.6864 MHz
crystal to the XTALIN and XTALOUT pins. In
this case, the EXTCLK pin becomes an output,
and may be used to drive external devices. If this
is not required, power may be saved by disabling
the EXTCLK output. The CLKFR pin should be
connected to DGND, which causes the clock cir-
cuits to be configured for 3.6864 MHz operation.
The oscillator has a low power mode. This re-
duces the internal crystal loading capacitance on
XTALOUT and XTALIN. The selection of this
mode is via a bit in Control Register #4. Since
the loading capacitance is reduced, then the crys-
tal frequency will increase by approximately
0.03%.
Alternatively, a 3.6864 MHz clock may be input
into the EXTCLK pin, in which case XTALIN
must be grounded, and XTALOUT is left float-
ing. The CLKFR pin must be connected to
DGND.
If only a 1.8432 MHz clock is available, then it
may be input into the EXTCLK pin and the
CLKFR pin connected to VD+. This causes the
CS8130 to double the incoming 1.8432 MHz
clock to 3.6864 MHz for internal use. XTALIN
must be grounded, and the XTALOUT pin is left
floating.
The CS8130 automatically sets the direction of
the EXTCLK pin. If the crystal oscillator is run-
ning when RESET goes high, then EXTCLK
becomes an output. Since the crystal oscillator
can take up to 25 ms to start, then it follows that
RESET must be held low, with PWRDN high
and power applied, for at least 25 ms. If using an
external clock, then RESET low can be short
(>1
s).
Power Down
When the PWRDN pin is brought low, all inter-
nal logic is stopped, including the crystal
oscillator. The power consumption in power
down mode is very low (<1
A). When the
PWRDN pin is brought high, the crystal oscilla-
tor will start. If using the crystal oscillator, allow
25 ms for oscillator start up after bringing
PWRDN high, before trying to use the CS8130.
The control register status will not be changed
by toggling PWRDN.
Control Register #1 allows for individual dis-
abling and enabling of the transmit and receive
sections of the CS8130.
The CS8130 also goes into power down if both
transmit enable and receive enable bits are false,
and the D/C pin is brought high. This allows
control of power down in a pod environment,
where access to the PWRDN pin is difficult. In
this mode, it is possible to select, via a control
register bit, whether the crystal oscillator remains
running, or is powered off. If the oscillator re-
mains running, then it consumes power, but
offers instant wake up. If the oscillator is pow-
ered off, then it consumes no power, but will
take 25 ms to start up.
The PWRDN pin must always be 鈥檋igh鈥� or
鈥檒ow鈥�. If this pin is allowed to float, excessive
power consumption may occur. All other digital
inputs may be allowed to float without causing
excessive power consumption in the CS8130 in
power down mode.
The RXD and FORM/BSY output pins may be
programmed to be high, low or float in power
down. This allows maximum flexibility in differ-
ent applications.
CS8130
DS134PP2
11
CS8130
DS134F1
11
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| CS8130-CSR | 鍔熻兘鎻忚堪:绱呭鏀剁櫦(f膩)鍣� IC Multi-Standard Infrared Transceiver RoHS:鍚� 鍒堕€犲晢:Vishay Semiconductors 娉㈤暦(zh菐ng):900 nm 閫ｇ簩(x霉)鏁�(sh霉)鎿�(j霉)鍌宠几:115.2 Kbit/s 鍌宠几璺濋洟:1 m 杓诲皠寮�(qi谩ng)搴�:60 mW/sr 鍗婂挤(qi谩ng)搴﹁搴�:44 deg 鑴堟矕瀵害:2 us 鏈€澶т笂鍗囨檪(sh铆)闁�:100 ns 鏈€澶т笅闄嶆檪(sh铆)闁�:100 ns LED 闆绘簮闆诲:- 0.5 V to 6 V 鏈€澶ф鍚戦浕娴�:80 mA 宸ヤ綔闆诲:2.4 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 25 C 灏哄:6 mm x 3.1 mm x 1.9 mm 灏佽 / 绠遍珨: 灏佽:Reel |
| CS8130-CSZ | 鍔熻兘鎻忚堪:绱呭鏀剁櫦(f膩)鍣� IC Multi-Standard Infrared Transceiver RoHS:鍚� 鍒堕€犲晢:Vishay Semiconductors 娉㈤暦(zh菐ng):900 nm 閫ｇ簩(x霉)鏁�(sh霉)鎿�(j霉)鍌宠几:115.2 Kbit/s 鍌宠几璺濋洟:1 m 杓诲皠寮�(qi谩ng)搴�:60 mW/sr 鍗婂挤(qi谩ng)搴﹁搴�:44 deg 鑴堟矕瀵害:2 us 鏈€澶т笂鍗囨檪(sh铆)闁�:100 ns 鏈€澶т笅闄嶆檪(sh铆)闁�:100 ns LED 闆绘簮闆诲:- 0.5 V to 6 V 鏈€澶ф鍚戦浕娴�:80 mA 宸ヤ綔闆诲:2.4 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 25 C 灏哄:6 mm x 3.1 mm x 1.9 mm 灏佽 / 绠遍珨: 灏佽:Reel |
| CS8130-CSZR | 鍔熻兘鎻忚堪:绱呭鏀剁櫦(f膩)鍣� IC Multi-Standard Infrared Transceiver RoHS:鍚� 鍒堕€犲晢:Vishay Semiconductors 娉㈤暦(zh菐ng):900 nm 閫ｇ簩(x霉)鏁�(sh霉)鎿�(j霉)鍌宠几:115.2 Kbit/s 鍌宠几璺濋洟:1 m 杓诲皠寮�(qi谩ng)搴�:60 mW/sr 鍗婂挤(qi谩ng)搴﹁搴�:44 deg 鑴堟矕瀵害:2 us 鏈€澶т笂鍗囨檪(sh铆)闁�:100 ns 鏈€澶т笅闄嶆檪(sh铆)闁�:100 ns LED 闆绘簮闆诲:- 0.5 V to 6 V 鏈€澶ф鍚戦浕娴�:80 mA 宸ヤ綔闆诲:2.4 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 25 C 灏哄:6 mm x 3.1 mm x 1.9 mm 灏佽 / 绠遍珨: 灏佽:Reel |
| CS8130-IS | 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪:IRDA TX/RX 0.1152MBPS 2.7V TO 5.5V 20SSOP - Rail/Tube |
| CS8130-ISR | 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪:IRDA TX/RX 0.1152MBPS 2.7V TO 5.5V 20SSOP - Tape and Reel |
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