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參數(shù)資料
| 型號(hào)： | CS5661EDW16 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | High Performance Dual Channel Current Mode Controller with ENABLE |
| 中文描述： | 高性能雙通道電流模式控制器，用ENABLE |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 167K |
| 代理商： | CS5661EDW16 |
5
The CS5661 is a high performance, fixed frequency, dual
channel current mode PWM controller for Off-Line and
DC to DC converter applications. Each channel contains a
high gain error amplifier, current sensing comparator,
pulse width modulator latch, and totem pole output driv-
er. The oscillator, reference, and undervoltage lockout cir-
cuits are common to both channels.
The oscillator has both precise frequency and duty cycle
control. The oscillator frequency is programmed by the
timing components R
T
and C
T
. Capacitor C
T
is charged
and discharged by an equal magnitude internal current
source and sink that generates a symmetrical 50 percent
duty cycle waveform at C
T
. The oscillator peak and valley
thresholds are 3.5V and 1.6V respectively. The source/
sink current is controlled by resistor R
T
. For proper opera-
tion over temperature range R
T
’s value should be between
4.0k
to 16k
.
As C
T
charges and discharges, an internal blanking pulse
is generated that alternately drives the inputs of the upper
and lower NOR gates high. This, in conjunction with a
precise amount of delay time introduced into each chan-
nel, produces well defined non-overlapping output duty
cycles. Output 2 is enabled while C
T
is charging, and
Output 1 is enabled during the discharge. Even at 500kHz,
each output is capable of approximately 44% duty cycle,
making this controller suitable for high frequency power
conversion applications.
In noise sensitive applications it may be necessary to syn-
chronize the converter with an external system clock. This
can be accomplished by applying an external clock signal.
For reliable synchronization, the oscillator frequency
should be set about 10% slower than the clock frequency.
The rising edge of the clock signal applied to SYNC, termi-
nates the charging of C
T
and V
OUT2
conduction. By tailor-
ing the clock waveform symmetry, accurate duty cycle
clamping of either output can be achieved.
Each channel contains a fully-compensated error amplifier
with access to the output and inverting input. The amplifi-
er features a typical dc voltage gain of 100 dB, and a unity
gain bandwidth of 1.0 MHz with 71 degrees of phase mar-
gin. The non-inverting input is internally biased at 2.5V.
The converter output voltage is typically divided down
and monitored by the inverting input through a resistor
divider. The maximum input bias current is -1.0 μA which
will cause an output voltage error that is equal to the
product of the input bias current and the equivalent input
divider resistance.
Its output voltage is offset by two diode drops (
≈
1.4V) and
divided by three before it connects to the inverting input
of the current sense comparator. This guarantees that both
Operating Description
C
Typical Performance Characteristics: continued
0
20
40
60
80
100
120
I
ref
, REFERENCE SOURCE CURRENT (mA)
-24
-20
-16
-12
-8.0
-4.0
0
R
,
V
V
CC
= 15V
T
A
= –55
°
C
T
A
= 125
°
C
T
A
=
25
°
C
-55
-25
0
25
50
75
100
125
T
A
, AMBIENT TEMPERATURE (
°
C)
I
S
,
S120
100
80
60
Reference Short Circuit Current vs. Temperature
Reference Voltage Change vs. Source Current
(LOAD TO GROUND)
V
=15V
80
μ
S PULSED LOAD
120Hz RATE
T
A
=25
°
C
T
A
= –55
°
C
T
A
= –55
°
C
T
A
=25
°
C
SINK
(LOAD TO V
CC
)
GND
0
200
OUTPUT LOAD CURRENT (mA)
400
600
800
V
s
,
S
V
CC
0
-1.0
-2.0
2.0
1.0
0
8.4
V
CC,
SUPPLY VOLTAGE (V) - CS-5661
0
8.0
16
24
32
R
T
=8.2k
C
T
=3.3nF
V
FB
1, 2=0V
CURRENT SENSE 1, 2=0V
T
A
=25
°
C
I
C
Supply Current vs. Supply Voltage
Output Saturation Voltage vs. Load Current
Oscillator
Error Amplifier
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