參數(shù)資料
型號: CS5560-ISZR
廠商: Cirrus Logic Inc
文件頁數(shù): 3/4頁
文件大小: 0K
描述: IC ADC 24BIT DELTA-SIGMA 24-SSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
采樣率(每秒): 50k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 85mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極;1 個差分,雙極
配用: 598-1277-ND - KIT BOARD FOR CDB5560 ADC
598-1273-ND - DEV BOARD FOR CS5560 W/MUX
AN311REV1
3
AN313
Figure 2 shows the timing of the RDY/, SCLK, and SDO signals from the A/D converter.
Figure 2. CS556x/7x/8x Serial Data Output Signals
4. Minimizing EMI
There are applications where output data from a converter must pass via a cable to another circuit board assembly.
If this is required, each active signal should have its own ground wire “partner”. On a connecter, such as a dual row
stake header, each active signal should be paired with a ground signal. Any connecting cable should be constructed
from twisted pair ribbon cable where each active signal has its own ground “partner” which is the other wire in the
twisted pair. This minimizes radiated noise and reduces the likelihood that radiated noise will interfere with converter
performance. It aslo enhances the likelihood that the system will pass any EMC (electromagnetic compatibility) re-
quirements.
This wiring method is illustrated in Figure 3.
Figure 3. Recommended Connector & Cable Configuration
RDY
SCLK(o)
SDO
MSB
MSB–1
LSB
LSB+1
D0
D23
D1
D21
D22
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