valid conversion due to the modified Sinc4 filter cha" />
參數(shù)資料
型號： CS5513-BSZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 11/26頁
文件大?。?/td> 0K
描述： IC ADC 20BIT INTERNAL OSC 8-SOIC
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 20
采樣率（每秒）： 326
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.7mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，雙極
CS5510/11/12/13
DS337F4
19
valid conversion due to the modified Sinc4 filter
characteristics.
2.5.5
Multiplexed Applications
The settling performance of the CS5510/11/12/13
in multiplexed applications is determined by the
Sinc4 filter. To settle, a step input requires 4 full
conversion cycles after the analog input has
switched. In this case, the throughput is reduced
by a factor of four as the first three conversions af-
ter the step is applied will not be fully settled.
If the application does not require the maximum
throughput possible from the ADC, the multiplexer
can be switched at any time. In this case, the sys-
tem must wait for at least five conversion cycles for
a fully-settled result from the ADC.
If maximum throughput is required in a multiplexed
application, the multiplexer must be switched at the
correct time during the data collection process. For
maximum throughput with the CS5510/12, switch-
ing of a multiplexer should occur 595 SCLK cycles
after SDO falls. For maximum throughput with the
CS5511/13, switching of a multiplexer should oc-
cur on the rising edge of SDO during a conversion
in which the data word is not read. The conversion
data that is immediately available when SDO falls
again is valid, and represents the analog input from
the previous multiplexer setting. The next three
conversions from the part will be unsettled values,
and the fourth conversion will represent a fully-set-
tled result from the new multiplexer setting. The
multiplexer should be switched again at the appro-
-140
-120
-100
-80
-60
-40
-20
0
020
40
60
80
100
120
Frequency (Hz)
M
a
gni
tu
d
e
(
d
B
)
47 Hz
63 Hz
CS5510/12
SCLK = 32.768 kHz
Figure 20. Digital Filter Response.
Frequency
(Hz)
Rejection
(dB)
Frequency
(Hz)
Rejection
(dB)
Frequency
(Hz)
Rejection
(dB)
Frequency
(Hz)
Rejection
(dB)
38
37
47
84
56
91
65
73
39
48
92
57
109
66
69
40
42
49
88
58
94
67
66
41
46
50
92
59
89
68
64
42
49
51
105
60
88
69
63
43
54
52
89
61
92
70
61
44
58
53
86
62
104
71
60
45
64
54
85
63
84
-
46
72
55
87
64
77
-
Table 4. Digital Filter Response at 32.768 kHz.
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