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參數(shù)資料
| 型號： | CS5422GDR16 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 116K |
| 代理商： | CS5422GDR16 |
CS5421
http://onsemi.com
7
threshold and the artificial ramp, the PWM comparator
terminates the initial pulse.
Figure 4. Idealized Waveforms
8.6 V
0.45 V
V
IN
V
COMP
V
FB
GATE(H)1
GATE(H)2
UVLO
STARTUP
NORMAL OPERATION
t
S
Normal Operation
During normal operation, the duty cycle of the gate drivers
remains approximately constant as the V
2
control loop
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load
conditions will result in changes in duty cycle to maintain
regulation.
Gate Charge Effect on Switching Times
When using the onboard gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading,
according to the following graphs.
Figure 5. Average Rise and Fall Times
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
5
6
7
8
Load (nF)
F
Average Fall Time
Average Rise Time
Transient Response
The 200 ns reaction time of the control loop provides fast
transient response to any variations in input voltage and
output current. Pulse–by–pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
Out–of–Phase Synchronization
In out–of–phase synchronization, the turn–on of the
second channel is delayed by half the switching cycle. This
delay is supervised by the oscillator, which supplies a clock
signal to the second channel which is 180
°
out of phase with
the clock signal of the first channel.
The advantages of out–of–phase synchronization are
many. Since the input current pulses are interleaved with one
another, the overlap time is reduced. The effect of this
overlap reduction is to reduce the input filter requirement,
allowing the use of smaller components. In addition, since
peak current occurs during a shorter time period, emitted
EMI is also reduced, thereby reducing shielding
requirements.
Overvoltage Protection
Overvoltage Protection (OVP) is provided as a result of
the normal operation of the V
2
control method and requires
no additional external components. The control loop
responds to an overvoltage condition within 200 ns, turning
off the upper MOSFET and disconnecting the regulator
from its input voltage. This results in a crowbar action to
clamp the output voltage preventing damage to the load. The
regulator remains in this state until the overvoltage
condition ceases.
Remote Sense
When the load is far away from the regulator, the long
feedback traces can cause additional voltage drop and
induce noise which affects the accuracy of voltage
regulation. A separate signal ground is provided to improve
the noise immunity of remote voltage sensing. The 1.0 V
reference voltage of the error amplifiers is directly
referenced to this ground and no large currents flow through
this ground during normal operation. The noise immunity
and regulation accuracy can be improved significantly.
Output Enable
On/Off control of the regulator outputs can be
implemented by pulling the COMP pins low. The COMP
pins must be driven below the 0.4 V PWM comparator offset
voltage in order to disable the switching of the GATE
drivers.
DESIGN GUIDELINES
Definition of the design specifications
The output voltage tolerance can be affected by any or all
of the following reasons:
1. buck regulator output voltage setpoint accuracy;
2. output voltage change due to discharging or charging
of the bulk decoupling capacitors during a load
current transient;
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