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| 型號(hào)： | CS5422GD16 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | CS5422GD16 |
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CS5421
http://onsemi.com
12
where:
P
GATE(L)
= lower MOSFET gate driver (IC) losses;
Q
GATE(L)
= total lower MOSFET gate charge at V
CC
;
f
SW
= switching frequency;
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
Adding External Slope Compensation
Today’s voltage regulators are expected to meet very
stringent load transient requirements. One of the key factors
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that very little
voltage ramp exists at the control IC feedback pin (V
FB
),
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the
internal slope compensation is insufficient, the performance
of the CS5421–based regulator can be improved through the
addition of a fixed amount of external slope compensation
at the output of the PWM Error Amplifier (the COMP pin)
during the regulator off–time. Referring to Figure 7, the
amount of voltage ramp at the COMP pin is dependent on the
gate voltage of the lower (synchronous) FET and the value
of resistor divider formed by R1and R2.
VSLOPECOMP
VGATE(L)
R2
R1
R2
(1.0
e
–t
)
where:
V
SLOPECOMP
= amount of slope added;
V
GATE(L)
= lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t
ON
or t
OFF
(switch off–time);
τ
= RC constant determined by C1 and the parallel
combination of R1, R2 neglecting the low driver
output impedance.
The artificial voltage ramp created by the slope
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off–time cycle duration (time during which the
lower MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin.
Figure 8. Small RC Filter Provides the Proper
Voltage Ramp at the Beginning of Each
On–Time Cycle
To Synchronous
FET
C1
R2
R1
CS5421
GATE(L)
COMP
C
COMP
THERMAL MANAGEMENT
Thermal Considerations for Power MOSFET
As the plastic packaging of a semiconductor will
deteriorate at high temperatures, it is necessary to limit the
junction temperature of the control IC and power MOSFETs
to maintain high reliability. Most semiconductor devices
have a maximum junction temperature of 150
°
C, and
manufacturers recommend operating their products at lower
temperatures if at all possible.
Power dissipation in a semiconductor devices results in
the generation of heat in the pin junctions at the surface of
the chip. This heat is transferred to the surface of the IC
package, but a thermal gradient exists due to the resistive
properties of the package molding compound. The
magnitude of the thermal gradient is expressed in
manufacturer’s data sheets as
Θ
JA
, or junction–to–air
thermal resistance. The on–chip junction temperature can be
calculated if
Θ
JA
, the air temperature at the surface of the IC,
and the on–chip power dissipation are known.
TJ
TA
(PD JA)
where:
TJ = IC or FET junction temperature (in degrees C);
TA = ambient temperature (in degrees C);
PD = power dissipated by part in question (in watts);
Θ
JA
= junction–to–ambient thermal resistance (in degrees
C per watt).
The value for
Θ
JA
can be found in the Absolute Maximum
Ratings table on page 2 of this datasheet. Note that this
value is different for every package style and every
manufacturer.
The junction temperature should be calculated for all
semiconductor devices as a part of the design phase in order
to ensure that the devices are operated below the
manufacturer’s
maximum
specification. If any component’s temperature exceeds the
manufacturer’s maximum temperature, some form of
heatsink will be required.
Heatsinking improves the thermal performance of any
component. Adding a heatsink will reduce the magnitude of
Θ
JA
by providing a larger surface area for the transfer of heat
from the component to the surrounding air. Typical
heatsinking techniques include the use of commercial
heatsinks for devices in TO–220 packages, or printed circuit
board techniques such as thermal bias and large copper foil
areas for surface mount packages.
When choosing a heatsink, it is important to realize that
Θ
JA
is comprised of several components:
JA
JC
junction
temperature
CS
SA
where:
Θ
JC
= the junction–to–case thermal resistance (in degrees
C per watt);
Θ
CS
= the case–to–sink thermal resistance (in degrees C
per watt);
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