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參數(shù)資料
| 型號(hào)： | CS5376 |
| 元件分類： | 串行ADC |
| 英文描述： | CS5376 Rev. A Errata|Geophysical|A/D Converters |
| 中文描述： | CS5376版本A勘誤表|地球物理| A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 171K |
| 代理商： | CS5376 |
2
ER256A1
Requested Output SD Port Configuration
When using the SD port in a requested output configuration, a single pulse to the SDTKI
pin initiates an SD port transaction. The pulse is generated by a controller that schedules
the data into the communication network. Because data is requested only when the
controller is ready to receive, local data buffering between the CS5376 and the
communication network is not required.
When an SD port transaction is completed, the SDTKO output pin automatically generates
a pulse that can trigger the SDTKI pin of another CS5376. In this way a pulse ‘token’
started by the communications controller can pass through a series of daisy-chained
CS5376 devices, initiating SD port transactions in each. The final CS5376 SDTKO output
can be returned to the controller to signal the end of a polling cycle.
1.1 Erratum Description
A timing constraint in the SD port was discovered during initial testing of CS5376 rev A.
The signal that initiates an SD port transaction, SDTKI, is required to arrive with a certain
timing relative to the internal decimation engine clock.
1.2 Erratum Work Around
Depending how the SD port is used in a design, either in the continuous output
configuration or the requested output configuration, two simple methods are available to
work around the SDTKI timing constraint. Both solutions use an inverted MCLK or
MCLK/2 signal to establish valid timing for the SDTKI rising edge. The continuous output
configuration work around is used on the CDB5372-76 rev A.0 evaluation board.
Continuous Output SD Port Configuration
To work around the SDTKI timing constraint when using the continuous output SD port
configuration, an inverted MCLK or MCLK/2 clock signal is used as the rising edge
source. For designs using an FPGA, the inverted MCLK or MCLK/2 signal is ANDed with
the SDRDY signal and connected to the SDTKI input as shown in Figure 1. The inverter
and AND gate are programmed into the FPGA, requiring the MCLK or MCLK/2 signal
and the SDRDY signal to be supplied as inputs.
CS5376
SDTKI
(Pin 64)
SDRDY
(Pin 61)
MCLK (Pin 13)
or MCLK/2 (Pin 12)
FPGA
Figure 1. Continuous output configuration SDTKI work around using an FPGA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CS5376A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, Multi-channel Decimation Filter |
| CS5376A_05 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, Multi-channel Decimation Filter |
| CS5376A_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, Multi-channel Decimation Filter |
| CS5376A-IQ | 功能描述:特殊用途放大器 LP Multi-Ch. Decimation Filter RoHS:否 制造商:Texas Instruments 通道數(shù)量:Single 共模抑制比（最小值）: 輸入補(bǔ)償電壓: 工作電源電壓:3 V to 5.5 V 電源電流:5 mA 最大功率耗散: 最大工作溫度:+ 70 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-20 封裝:Reel |
| CS5376A-IQR | 功能描述:特殊用途放大器 LP Multi-Ch. Decimation Filter RoHS:否 制造商:Texas Instruments 通道數(shù)量:Single 共模抑制比（最小值）: 輸入補(bǔ)償電壓: 工作電源電壓:3 V to 5.5 V 電源電流:5 mA 最大功率耗散: 最大工作溫度:+ 70 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-20 封裝:Reel |
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