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參數(shù)資料
| 型號(hào)： | CS5371A-ISZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 10/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MODULATOR LP/HP 1CH 24-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 調(diào)制器 |
| 分辨率（位）： | 24 b |
| 采樣率（每秒）： | 512k |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | ±2.5V，3.3 V ~ 5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | 598-1778-ND - EVALUATION BOARD FOR CS5376 |
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CS5371A CS5372A
18
DS748F3
5. DIGITAL SIGNALS
The CS5371A and CS5372A modulators are
designed to operate with the CS5376A digital
filter. The digital filter generates the modulator
clock and synchronization signals (MCLK and
MSYNC) while receiving back the modulator
one-bit
ΔΣ conversion data and over-range
flag (MDATA and MFLAG).
5.1 MCLK Connection
The CS5376A digital filter generates the mas-
ter clock for CS5371A and CS5372A, typically
2.048 MHz, from a synchronous clock input
from the external system. If MCLK is disabled
during operation, the modulators will enter a
power down state after approximately 40
S.
By default, MCLK is disabled at reset and is
enabled by writing the digital filter CONFIG
register.
MCLK must have low jitter to guarantee full an-
alog performance, requiring a crystal- or
VCXO-based system clock input to the digital
filter. Clock jitter on the digital filter CLK input
directly translates to jitter on MCLK.
5.2 MSYNC Connection
The CS5376A digital filter also provides a syn-
chronization signal to the CS5371A and
CS5372A modulators. The MSYNC signal is
automatically generated following a rising
edge received on the digital filter SYNC input.
By default, MSYNC generation is disabled at
reset and is enabled by writing the digital filter
CONFIG register.
The input SYNC signal to the CS5376A digital
filter sets a common reference time t0 for mea-
surement events, thereby synchronizing ana-
log sampling across a measurement network.
The timing accuracy of the received SYNC sig-
nal from measurement node to measurement
node must be ±1 MCLK to maximize the
MSYNC analog sample synchronization accu-
racy.
CS5372A
ΔΣ Modulator
INF+
INR+
INF-
INR-
INF-
INR-
INF+
INR+
VREF+
VREF-
VA+
VA-
VD
GND
MDATA1
MFLAG1
MDATA2
MFLAG2
MCLK
MSYNC
PWDN1
OFST
PWDN2
VREF
2.5 V
VA+
VA-
10
Ω
0.01
μF
VD
CS5376A
Digital Filter
VDD2
GND
MDATA1
MFLAG1
MDATA2
MFLAG2
MCLK
MSYNC
GPIO
VA+
0.1
μF
0.01
μF
VD
VA-
0.1
μF
20nF
C0G
20nF
C0G
680
CS3301A
CS3302A
AMPLIFIER
OUTR+
OUTF+
OUTF-
OUTR-
680
20nF
C0G
20nF
C0G
680
CS3301A
CS3302A
AMPLIFIER
OUTR+
OUTF+
OUTF-
OUTR-
680
VA+
VA-
VA+
VA-
100
μF
Figure 12. Digital Signals
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5371-BS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC LP High Performance Delta Sigma Mod. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5371-BSR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC LP High Performance Delta Sigma Mod. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5371-BSZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC LP Hgh Prfrmnc Delta Sigma Modultr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5371-BSZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC LP High Performance Delta Sigma Mod. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5372 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:LOW POWER HIGH PERFORMANCE MODULATORS |
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