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參數(shù)資料
| 型號： | CS5303GDWR28 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 176K |
| 代理商： | CS5303GDWR28 |
CS5303
http://onsemi.com
14
disabled or will only check that the applicable supply is on
– not that it is at a high enough voltage to run the converter.
For the 12 V
IN
converter in the application diagram on
page 2 the UVLO pin for the high side driver is pulled up
by the 5 V supply (through two diode drops) and the function
is not used. The diode between the COMP pin and the 12 V
supply holds the COMP pin near Gnd and prevents start–up
while the 12 V supply is off. In an application where a higher
UVLO threshold is necessary a circuit like the one in Figure
15 will lock out the converter until the 12 V supply exceeds
9 V.
Figure 15. External UVLO Circuit
COMP
100 k
100 k
50 k
+5 V
+12 V
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically a multi–layer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to reroute the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
Voltage feedback should be taken from a point of the
output or the output filter that doesn’t favor any one phase.
If the feedback connection is closer to one inductor than the
others the ripple associated with that phase may appear
larger than the ripple associated with the other phases and
poor current sharing can result.
The current sense signal is typically tens of milli–volts.
Noise pick–up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as switch nodes and gate drive signals. The paths
should be matched as well as possible. It is especially
important that all current sense signals be picked off at
similar points for accurate current sharing. If the current
signal is taken from a place other than directly at the inductor
any additional resistance between the pick–off point and the
inductor appears as part of the inherent inductor resistance
and should be considered in design calculations. Capacitors
for the current feedback networks should be placed as close
to the current sense pins as practical.
DESIGN PROCEDURE
Current Sensing, Power Stage and
Output Filter Components
1. Choose the output filter components to meet peak
transient requirements. The formula below can be
used to provide an approximate starting point for
capacitor choice, but will be inadequate to calculate
actual values.
VPEAK
( I
T)
ESL
I
ESR
Ideally the output filter should be simulated with
models including ESR, ESL, circuit board parasitics
and delays due to switching frequency and converter
response.
Typically
both
(electrolytic, Oscon, etc,) and low impedance
capacitance (ceramic chip) will be required. The bulk
capacitance provides “hold up” during the converter
response. The low impedance capacitance reduces
steady state ripple and bypasses the bulk capacitance
during slewing of output current.
2. For inductive current sensing (only) choose the
current sense network RC to provide a 25 mV
minimum ramp during steady state operation.
bulk
capacitance
R
(VIN
VOUT)
VOUTVIN
C
F
25 mV
Then choose the inductor value and inherent
resistance to satisfy L/R
L
= R
×
C.
For ideal current sense compensation the ratio of L
and R
L
is fixed, so the values of L and R
L
will be a
compromise typically with the maximum value R
L
limited by conduction losses or inductor temperature
rise and the minimum value of L limited by ripple
current.
3. For resistive current sensing choose L and R
S
to
provide a steady state ramp greater than 25 mV.
L RS
(VIN
VOUT)
TON25 mV
Again the ratio of L and R
L
is fixed and the values of
L and R
S
will be a compromise.
4. Calculate the high frequency output impedance
(ConverterZ) of the converter during transients. This
is the impedance of the Output filter ESR in parallel
with the power stage output impedance (PwrstgZ)
and will indicate how far from the original level
(
VR) the output voltage will typically recover to
相關PDF資料 |
PDF描述 |
|---|---|
| CS5345-KS | Analog-to-Digital Converter， 16-Bit |
| CS5349-BP | Analog-to-Digital Converter， 16-Bit |
| CS5349-BS | Analog-to-Digital Converter， 16-Bit |
| CS5349-KP | Analog-to-Digital Converter， 16-Bit |
| CS5349-KS | Analog-to-Digital Converter， 16-Bit |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS5305 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Three−Phase Synchronous Switching Step−Down Controller with Single Wire Current Sharing |
| CS5305/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Three-Phase Synchronous Switching Step-Down Controller with Single Wire Current Sharing |
| CS5305GDW28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| CS5305GDWR28 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Three−Phase Synchronous Switching Step−Down Controller with Single Wire Current Sharing |
| CS5307/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Four-Phase VRM 9.0 Buck Controller |
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