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參數(shù)資料
| 型號(hào)： | CS52843EDR8 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Current Mode PWM Control Circuit |
| 中文描述： | 電流模式PWM控制電路 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 147K |
| 代理商： | CS52843EDR8 |
When the power supply sees a sudden large output cur-
rent increase, the control voltage will increase allowing the
duty cycle to momentarily increase. Since the duty cycle
tends to exceed the maximum allowed to prevent trans-
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
Figure 2: Timing Diagram
Figure 3: Oscillator Timing Network and Parameters
Setting the Oscillator
The times T
c
and T
d
can be determined as follows:
(
t
c
= R
T
C
T
ln
t
d
= R
T
C
T
ln
Substituting in typical values for the parameters in the
above formulas:
V
REF
= 5.0V, V
UPPER
= 2.7V, V
LOWER
= 1.0V, I
d
= 8.3mA,
then
t
c
≈
0.5534R
T
C
T
t
d
= R
T
C
T
ln
For better accuracy R
T
should be
≥
10k
.
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.
The transistor and 5k
potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
)
2.3 - 0.0083 R
T
4.0 - 0.0083 R
T
(
)
V
REF
- I
d
R
T
- V
LOWER
V
REF
- I
d
R
T
- V
UPPER
(
)
V
REF
- V
LOWER
V
REF
- V
UPPER
V
CC
I
O
V
O
Switch
EA Output
F/F Toggle
OSC
RESET
V
OSC
5
C
Circuit Description
V
REF
OSC
Gnd
R
T
C
T
V
upper
V
lower
t
c
t
d
V
OSC
Internal Clock
LARGE R
T
(
≈
10k
)
V
REF
Internal Clock
SMALL R
T
(
≈
700k
)
Triangular Mode
Sawtooth Mode
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| CS52845ED14 | 制造商:CHERRY 制造商全稱:CHERRY 功能描述:Current Mode PWM Control Circuit with 50% Max Duty Cycle |
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