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參數(shù)資料
| 型號(hào)： | CS5166H |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | 5-Bit Synchronous CPU Controller with Power-Good and Current Limit |
| 中文描述： | 5位同步CPU，具有功率控制器，準(zhǔn)確和電流限制 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大小： | 435K |
| 代理商： | CS5166H |
C
20
1.325 1.375 1.425 1.475 1.525 1.575 1.625 1.675 1.725 1.775 1.825 1.875 1.925 1.975 2.025 2.075
DAC Output Voltage Setting (V)
O
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
Figure 31: Percent Output Error vs DAC Voltage Setting,
V
CC
= 12V, T
A
= 25
C, V
ID4
= 0.
Figure 34: Percent Output Error vs. DAC Output Voltage Setting
V
CC
= 12V, T
A
= 25
C, V
ID4
= 1.
Typical Performance Characteristics
Figure 30: GATE(H) & GATE(L) Falltime vs. Load Capacitance.
200
180
160
140
120
100
80
60
40
20
0
0
2000
4000
6000
Load Capacitance (pF)
8000
10000 12000 14000 16000
F
V
CC
=12V
T
A
=25C
Figure 33: DAC Output Voltage vs Temperature, DAC Code = 10111,
V
CC
= 12V.
120
100
80
60
40
20
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
Junction Temperature (
C)
D
0
200
180
160
140
120
100
80
60
40
20
0
0
2000
4000
6000
Load Capacitance (pF)
8000
10000
12000 14000 16000
V
CC
=12V
T
A
=25C
R
Figure 29: GATE(L) Risetime vs. Load Capacitance.
Figure 32: GATE(H) Risetime vs. Load Capacitance.
0
2000
4000
6000
Load Capacitance (pF)
8000 10000 12000 14000 16000
200
180
160
140
120
100
80
60
40
20
0
R
V
CC
=12V
T
A
=25C
2.125 2.225 2.3252.425 2.525 2.625 2.725 2.825 2.925 3.025 3.125 3.225 3.325 3.425 3.525
DAC Output Voltage Setting (V)
O
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
11) Place the V
FB
filter resistor in series with the
V
FB
pin (pin 16) right at the pin.
12) Place the V
FB
filter capacitor right at the V
FB
pin (pin
16).
13) The “Droop” Resistor (embedded PCB trace) has to be
wide enough to carry the full load current.
14) Place the V
CC
bypass capacitor as close as possible to
the V
CC
pin and connect it to the PGnd pin of the IC.
Connect the PGnd pin directly to the Gnd plane.
15) Create a subground (local Gnd) plane preferably on
the PCB top layer and under the IC controller. Connect all
logic capacitor returns and the LGnd pin of the IC to this
plane. Connect the subground plane to the main Gnd
plane using a minimum of four (4) vias.
Application Information: continued
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|---|---|
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