參數(shù)資料
型號(hào)： CS51313GD16
廠商： ZF Electronics Corporation
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Micropower 5V, 100mA Low Dropout Linear Regulator
中文描述： 微5V的，100mA的低壓差線性穩(wěn)壓器
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 248K
代理商： CS51313GD16
Application Information: continued
8
resistors determine the output voltage for each regulator.
In this case, it will be 1.5V @ 3A for V
GTL
and 2.5V @ 1A for
V
CLOCK
. In Figure 7 the ratio of resistor R1 to resistor R2 is
(V
OUT
/V
REF
) - 1, where V
OUT
= 1.5V and V
REF
= 1.23V. The
same formula can be used to determine the ratio of the
feedback resistors needed to implement a 2.5V linear regu-
lator (V
OUT
= 2.5V).To negate the bias current of the opera-
tional amplifier, a resistor with a value equal to the parallel
combination of the feedback resistors (R1//R2) is connect-
ed in series with the non-inverting input of this operational
amplifier. R2 sets the minimum output current, (I
MIN
=
V
REF
/R2).
The pass transistor must be able to dissipate the power
adequately while keeping the junction temperature below
the maximum specified by the manufacturer. For example,
with V
GTL
output of 1.5V, input voltage of 3.3V, and out-
put DC current of 3A, the pass transistor dissipates (3.3V -
1.5V)
×
3A = 5.4W.
Sufficient output capacitance must be added to ensure that
the output voltage remains within specification during
transient loading. For example, the GTL bus load can ramp
from 0 to 2.7A at a rate of 8A/μs. The designer needs to
verify that the circuit will meet these requirements using
the transistor and operational amplifier chosen.
Startup
The CS51313 provides a controlled startup of regulator out-
put voltage and features Programmable Soft Start imple-
mented through the Error Amp and external Compensation
Capacitor. This feature, combined with overcurrent protec-
tion, prevents stress to the regulator power components
and overshoot of the output voltage during startup.
As Power is applied to the regulator, the CS51313
Undervoltage Lockout circuit (UVL) monitors the IC’s sup-
ply voltage (V
CC
) which is typically connected to the +12V
output of the AC-DC power supply. The UVL circuit pre-
vents the NFET gates from being activated until V
CC
exceeds the 8.4V (typ) threshold. Hysteresis of 300mV (typ)
is provided for noise immunity. The Error Amp Capacitor
connected to the COMP pin is charged by a 30μA current
source. This capacitor must be charged to 1.1V (typ) so that
it exceeds the PWM comparator’s offset before the V
2
TM
PWM control loop permits switching to occur.
When V
CC
has exceeded 8.4V and COMP has charged to
1.1V, the upper Gate driver (GATE(H)) is activated, turn-
ing on the upper FET. This causes current to flow through
the output inductor and into the output capacitors and
load according to the following equation:
I = (V
IN
– V
OUT
)
×
GATE(H) and the upper NFET remain on and inductor
current ramps up until the initial pulse is terminated by
either the PWM control loop or the overcurrent protection.
This initial surge of in-rush current minimizes startup time,
but avoids overstressing of the regulator’s power compo-
nents.
The PWM comparator will terminate the initial pulse if the
regulator output exceeds the voltage on the COMP pin
plus the 1.1V PWM comparator offset before the voltage
drop across the current sense resistor exceeds the current
limit threshold voltage. In this case, the PWM control loop
has achieved regulation and the initial pulse is then fol-
lowed by a constant off time as programmed by the C
OFF
capacitor. The COMP capacitor will continue to slowly
charge and the regulator output voltage will follow it, less
the 1.1V PWM offset, until it achieves the voltage pro-
grammed by the DAC’s VID input. The Error Amp will
then source or sink current to the COMP cap as required to
maintain the correct regulator DC output voltage. Since the
rate of increase of the COMP pin voltage is typically set
much slower than the regulator’s slew capability, inrush
current, output voltage, and duty cycle all gradually
increase from zero. (See Figures 8, 9, and 10).
Figure 8: Normal Startup (2ms/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 - COMP Pin (1V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Figure 9: Normal Startup showing initial pulse followed by Soft Start
(20μs/div).
Channel 1 - Regulator Output Voltage (0.2V/div)
Channel 2 – Inductor Switching Node (5V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Start-up @
V
CC
> 8.4V
Initial Pulse until V
> COMP + PWM Offset
Start-up @
V
CC
> 8.4V
T
L
C
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