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參數(shù)資料
| 型號(hào)： | CS5127GDW16 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Dual Output Nonsynchronous Buck Controller with Sync Function and Second Channel Enable |
| 中文描述： | 非同步雙輸出同步降壓控制器的功能及第二通道啟用 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | CS5127GDW16 |
Applications Information: continued
where T
SOFT START
is given in seconds if C
COMP
is given in
farads, I
COMP(SOURCE)
in amperes, and V
FFB
in volts. Note
that a design trade off will be made in choosing the value
of the COMP lead capacitor. Larger values of capacitance
will result in better regulation and improved noise immu-
nity, but the soft start interval will be longer and capacitor
price may increase.
Figure 5: Measured performance of the CS5127 at start up.
C
COMP
=100μF, I
COMP(SOURCE)
=1.3mA, V
FFB
= 2.8V, T
SOFTSTART
= 0.22s.
During normal operation, the gate driver switching duty
cycle will remain approximately constant as the V
2
acon-
trol loop maintains the regulated output voltage under
steady state conditions. Changes in supply line or output
load conditions will result in changes in duty cycle to
maintain regulation.
Voltage Mode Operation
There are two methods by which a user can operate the
CS5127 in voltage mode. The first method is simple, but
the transient response is typically very poor. This method
uses the same components as V
2
aoperation, but by
increasing the amplitude of the artificial ramp signal, V
2
a
control is defeated and the controller operates in voltage
mode. Calculate RR using the formula above and divide
the value obtained by 10. This should provide an ade-
quately large artificial ramp signal and cause operation
under voltage mode control. There may be some depen-
dence on board layout, and further optimization of the
value for RR may be done empirically if required.
Voltage mode control may be refined by removing the
COMP pin capacitor and adding a two pole, one zero com-
pensation network. Consider the system block diagram
shown in figure 6.
Figure 6: Voltage mode control equivalent circuit with two pole, one
zero compensation network.
V
IN
is the switch supply voltage, R represents the load, RL
is the combined resistance of the FET RDS (on) and the
inductor DC resistance, L is the inductor value, C is the
output capacitance, RC is the output capacitor ESR, RA
and RB are the feedback resistors and VR is the peak to
peak amplitude of the artificial ramp signal at the V
FFB
pin. C1, C2, R1 and R2 are the components of the compen-
sation network. Based on the application circuit from page
1, values for the 2.8V output equivalent circuit are:
V
IN
= 5V
R =
RL =
C =
RC = 0.025
RA = 1540
RB =
L =
0.4
0.02
1320μF
1270
5μH
A resistor change is necessary to increase the artificial
ramp magnitude to V
FFB1
. Changing R10 from 20k to 2k
will give a peak to peak amplitude of about 2V. Thus, V
R
=
2V.
The transfer function from V
CONTROL
to V
OUT
is
V
OUT
V
CONTROL
=
′
Using the component values provided, this reduces to
1
V
R
R
′
V
IN
′
(sCR
C
+ 1)
s
2
LC (R + R
C
) + s[L + R
L
C(R + R
C
) + RCR
C
] + R + R
C
V
IN
L
R
L
C
R
C
R
R
A
R
B
R1
R2
C1
C2
PWM
EA
1.275V
V
CONTROL
V
R
V
OUT
V
FB
V
FFB
COMP
CONTROL
LOGIC
Voltage Mode Control
Normal Operation
11
C
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