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參數(shù)資料
| 型號(hào)： | CS5112EDWFR24 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | 1.4A Switching Regulator with 5V, 100mA Linear Regulator with Watchdog, RESET and ENABLE |
| 中文描述： | 1.4A的開關(guān)穩(wěn)壓器采用5V，100mA的線性穩(wěn)壓器，帶有看門狗，復(fù)位和啟用 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 199K |
| 代理商： | CS5112EDWFR24 |
9
C
Application Notes: continued
25
0
0
5
V
REG
(V)
50
75
100
10
20
25
I
L
15
30
Q
JA
= 35
°
C/W
V
IN
= 14V
Max Total Power = 1.86W
25
0
0
5
V
REG
(V)
50
75
100
10
20
25
I
L
15
30
Q
JA
= 55
°
C/W
V
IN
= 14V
Max Total Power = 1.18W
Linear Regulator Output Current vs. Input Voltage
* Subjecting the CS5112 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal limit.
Figure 10. Bode plot of error amplifier (OTA) gain and modulator gain
added to the feedback resistor divider attenuation.
A pole at point C:
f
p
= 1/(1R
4
C
2
),
(8g)
offsets the zero set by the ESR of the output capacitors.
An alternative scheme uses a single capacitor as shown in
Figure 11, to roll the gain off at a relatively low frequency.
Figure 11. A typical application diagram with external components con-
figured in a boost topology.
Step 9
Finally the watchdog timer period and Power on Reset
time is determined by:
t
Delay
= 1.353
′
C
Delay
R
BIAS
.
(9)
V
IN
NC
NC
V
SW
Gnd
Gnd
Gnd
Gnd
V
FB1
V
FB2
SELECT
COMP
V
REG
V
LIN
I
BIAS
Gnd
Gnd
Gnd
Gnd
C
Delay
WDI
C
OSC
R
BIAS
W
100
F
ESR<8
W
0.1
m
F
C
0.33
m
F
L=33
m
H
V
IN
C
OUT
88
m
F
(2)
100k
W
946
W
7.5k
W
R
1
R
2
R
3
C
delay
390pF
C
OSC
C
RESET
ENABLE
(1)
V
OUT
= 18V, Select > 2V
V
OUT
= 16V, Select < 0.8V
MICROPROCESSOR
5V
Pole due to error amplifier
output impedance and C
1
G
0
f
z
= 1/2
p
R4C1
+G
B
A
C
f
P
= 1/
p
R
Load
C
OUT
error amplifier gain
f
CO
f
z
= 1/2
p
ESR C
OUT
f
P
= 1/
p
R
4
C
2
-20dB/dec
-G
G
modulator gain + feedback resistor divider attenuation
Worst Case Switcher
Power Available
(
Q
JA
= 55C/W)
(W)
0.74
0.35
*
*
0.58
0.07
*
*
Worst Case Switcher
Power Available
(
Q
JA
= 35C/W)
(W)
1.42
1.03
0.64
0.26
1.26
0.75
0.24
*
Linear Power
Dissipation
(W)
0.44
0.83
1.22
1.60
0.60
1.11
1.62
2.14
V
REG
(V)
20
20
20
20
25
25
25
25
V
IN
(V)
14
14
14
14
14
14
14
14
I
LIN
(mA)
25
50
75
100
25
50
75
100
Figure 12: The shaded area shows the safe operating area of the CS5112 as a function of I
LIN
, V
REG
, and
Q
JA
. Refer to the table below for typical
loads and voltages.
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