參數(shù)資料
型號(hào): CS495314-DVZ
廠商: Cirrus Logic Inc
文件頁數(shù): 19/19頁
文件大小: 0K
描述: IC DSP DECODER 32BIT 128-LQFP
標(biāo)準(zhǔn)包裝: 72
系列: *
其它名稱: 598-1944
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2
9
4.3.2 Termination Requirements
Open-drain pins on the CS4953xx must be pulled high for proper operation. Refer to the CS4953xx Hardware
User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper
operation.
Mode select pins on the CS4953xx are used to select the boot mode upon the rising edge of reset. A detailed
explanation of termination requirements for each communication mode select pin can be found in the
CS4953xx Hardware User’s Manual.
4.3.3 Pads
The CS4953xx I/O operates from the 3.3 V supply and is 5 V tolerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may
contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the
device.
5 Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and
temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C,
CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
Parameter
Symbol
Min
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
VDD
VDDA
VDDIO
–0.3
-
2.0
3.6
0.3
V
Input pin current, any pin except supplies
Iin
—+/- 10
mA
Input voltage on PLL_REF_RES
Vfilt
-0.3
3.6
V
Input voltage on I/O pins
Vinio
-0.3
5.0
V
Storage temperature
Tstg
–65
150
°C
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