
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705PP8
20
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode
Parameter
Symbol
Min
Typical
Max
Unit
Address setup before PCP_CS and PCP_DS low
tmas
5—
—
ns
Address hold time after PCP_CS and PCP_DS low
tmah
5—
—
ns
Read
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS# low
tmcdr
0—
—
ns
Data valid after PCP_CS and PCP_DS low with PCP_R/W high
tmdd
—
19
ns
PCP_CS and PCP_DS low for read
tmrpw
24
—
ns
Data hold time after PCP_CS or PCP_DS high after read
tmdhr
8—
—
ns
Data high-Z after PCP_CS or PCP_DS high after read
tmdis
—
18
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
read1
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing
the input data buffer. AN288 CS4953xx/CS497xxx Firmware User’s Manual should be consulted for the firmware
speed limitations.
tmrd
30
—
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
tmrdtw
30
—
ns
PCP_RW rising to PCP_IRQ falling
tmrwirqh
—
12
ns
Write
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
tmcdw
0—
—
ns
Data setup before PCP_CS or PCP_DS high
tmdsu
8—
—
ns
PCP_CS and PCP_DS low for write
tmwpw
24
—
ns
PCP_R/W setup before PCP_CS AND PCP_DS low
tmrwsu
24
—
ns
PCP_R/W hold time after PCP_CS or PCP_DS high
tmrwhld
8—
—
ns
Data hold after PCP_CS or PCP_DS high
tmdhw
8—
—
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with
PCP_R/W high for next re
ad1tmwtrd
30
—
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
tmwd
30
—
ns
PCP_RW rising to PCP_BSY falling
tmrwbsyl
—
2*DCLKP + 20
—
ns