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參數(shù)資料
| 型號(hào)： | CS4815 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | OC-48/12/3 DW/FEC/PM and ASYNC Mapper Device with Strong FEC |
| 中文描述： | OC-48/12/3倉庫/前向糾錯(cuò)/ PM和異步映射器設(shè)備具有強(qiáng)糾錯(cuò) |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 173K |
| 代理商： | CS4815 |
Empowering Intelligent Optical Networks
Product Brief
RUBICON-48
OC-48/12/3 DW/FEC/PM and ASYNC Mapper Device with Strong FEC
Part Number S4815PBI, Revision 2.2, May 2006
FINAL Information
- The information contained in this document is
about a product that has been fully tested, characterized, and is pro-
duction release. All features described herein are supported. Contact
AMCC for updates to this document and the latest product status.
FEATURES
Easy software migration from industry leading AMCC
NIAGARA FEC device
Significant reuse of the Niagara register map in Rubicon.
Superb migration path to lower power Rubicon-48 device.
Backwards compatible with AMCC’s industry leading
S3062 FEC device
FEC and Framing compatible between Rubicon-48 and S3062.
Superb migration path to better integration Rubicon-48 device.
G.709 ODU - 1 Synchronous and Asynchronous mapping
1 x OC – 48/STM-16 synchronous and asynchronous mapping
(239,238).
G.709 Overhead processing
Bi-directional add-drop ODU – 1.
Bi-direction G.709 Overhead Processing for bi-directional
OTU1 regeneration.
Dedicated GCC ports.
Ingress and Egress SONET/SDH Performance Monitoring/
Injection
1 x OC-/48/12/3 TOH add-drop and processing.
8B/10B Monitoring.
SONET/SDH section and line termination including full B2
recalculation.
TOH add-drop port.
LOS, OOF, LOF detection.
B1, B2 monitoring with programmable Signal Degrade and Sig-
nal Fail thresholds.
J0 Monitoring, SDH and SONET modes.
Support for Protection Switching.
K1, K2 monitoring for APS changes, line AIS and line RDI.
Automatic, interrupt-driven, or manual AIS insertion.
Frame boundary output.
Industry Standard RS(255,239)
F
orward
E
rror
C
orrection
with
6.2 dB Coding Gain
(at 10
-15
CER)
G.709 Compliant Frame Structure.
Compatible with AMCC’s S19203 (HUDSON) and S19208
(NIAGARA).
Limited backwards compatibility with AMCC’s S3062.
Enhanced Gain Forward Error Correction with G.709 ODU
2.7 Gbps enhanced FEC with > 8.6 dB coding gain.
G.709 overhead processing and nominal rate expansion.
Comprehensive channel statistics gathering including.
Corrected bits, bytes.
Corrected zeros, ones (with outputs).
Uncorrectable sub-frame count.
Broad Interface Compatibility
16-bit 155Mbps LVDS interface
4-bit 622Mbps LVDS interface
Compatible with AMCC’s DANUBE, MISSOURI, OHIO,
RHINE, VOLTA, S3465, S3457, S3455, S3086 and S3485.
Provides port swapping and output dual feed features for 1 + 1
line protection scheme.
Support For System Test and Diagnostics
Can synthesize SONET frames.
Error injection capability for verification of remote error report-
ing.
Test-set compliant pseudo-random sequence generation/anal-
ysis.
Client and Line side loopback.
General Purpose Processor Interface
Glueless 16-bit interface to MPC860, 25 MHz to 66 MHz. Dual
mode interface also supports Intel processors.
Interrupt driven or Polled mode operation.
Figure 1: Block Diagram
u P I/F
In te rfa c e
In te rfa c e
D e c o d e r
E n c o d e r
M a p
C o n tro l
T O H A d d /D ro p
F E C
D e c o d e r
E n c o d e r
E rr In s
A n a ly s is
P M
P M
E rr In s
A n a ly s is
A d d /D ro p
B Y P A S S
B Y P A S S
B Y P A S S
B Y P A S S
B Y P A S S
B Y P A S S
(2 .7 G b p s )
G b p s )
8 o r 1 6
O T N N e tw o rk /L in e
C lie n t o r O T N
E F E C
E F E C
R e g is te r
In te rru p t
S O N E T /S D H
R -S
F E C
P N g e n
& E rr
P N g e n
& E rr
O D U -1 O H
S F I-4
S F I-4 (2 .7
In g re s s E g re s s
R -S
P a tte rn
P a tte rn
In g re s s /E g re s s
O
O
A
A
O
A
O
A
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