(Inputs: Logic 0 = GND, Logic 1 = VLC, C
參數(shù)資料
型號: CS4364-CQZR
廠商: Cirrus Logic Inc
文件頁數(shù): 9/50頁
文件大?。?/td> 0K
描述: IC DAC 103DB 24BIT 6CH 48-LQFP
標準包裝: 2,000
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 模擬和數(shù)字
功率耗散(最大): 520mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 8 電壓,單極
采樣率(每秒): 216k
配用: CDB4364-ND - EVALUATION BOARD FOR CS4364
DS619F1
17
CS4364
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF)
Notes:
17. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For FSCK < 1 MHz.
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
s
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
tdh
15
-
ns
Rise Time of CCLK and CDIN
tr2
-100
ns
Fall Time of CCLK and CDIN
tf2
-100
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CC L K
CD IN
t css
t csh
t spi
t srs
RST
Figure 5. Control Port Timing - SPI Format
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