參數(shù)資料
型號(hào): CS4360-KZZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 24/37頁(yè)
文件大?。?/td> 0K
描述: IC DAC STER 6CH 102DB 28-TSSOP
標(biāo)準(zhǔn)包裝: 4,000
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 6
電壓電源: 模擬和數(shù)字
功率耗散(最大): 265mW
工作溫度: -10°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類(lèi)型: 6 電壓,單極
采樣率(每秒): 192k
CS4360
30
DS517F2
6.
REGISTER DESCRIPTIONS
Note: All registers are read/write in IC mode and write only in SPI, unless otherwise stated.
6.1
MODE CONTROL 1 (ADDRESS 01H)
6.1.1
AUTO-MUTE (AMUTE) BIT 7
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or 1. A single sample of non-static data will release the mute. Detection and muting
is done independently for each channel. The quiescent voltage on the output will be retained and the
Mute Control pin will become active during the mute period. The muting function is affected, similar
to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
6.1.2
DIGITAL INTERFACE FORMAT (DIF) BIT 4-6
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 15-17.
76543
210
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
FM1
FM0
10000
000
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
000
Left Justified, up to 24-bit data
001
I2S, up to 24-bit data
010
Right Justified, 16-bit data
011
Right Justified, 24-bit data
100
Right Justified, 20-bit data
101
Right Justified, 18-bit data
110
Reserved
--
111
Reserved
--
Table 8. Digital Interface Formats - Control Port Mode
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