FREEZE CONTROLS (FREEZE) BIT 2 Default = 0 0 - Disabled 1 - Enabled Function: T" />
參數(shù)資料
型號: CS4360-DZZR
廠商: Cirrus Logic Inc
文件頁數(shù): 29/37頁
文件大?。?/td> 0K
描述: IC DAC STER 6CH 102DB 28-TSSOP
標(biāo)準(zhǔn)包裝: 4,000
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 6
電壓電源: 模擬和數(shù)字
功率耗散(最大): 265mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 6 電壓,單極
采樣率(每秒): 192k
CS4360
DS517F2
35
6.5.5
FREEZE CONTROLS (FREEZE) BIT 2
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To have multiple changes in the control port registers take effect simulta-
neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
6.5.6
MASTER CLOCK DIVIDE ENABLE (MCLKDIV) BIT 1
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.
6.5.7
SINGLE VOLUME CONTROL (SNGLVOL) BIT 0
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. When enabled, the volume on all channels is determined by the
A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored.
6.6
REVISION REGISTER (READ ONLY) (ADDRESS 0DH)
6.6.1
REVISION INDICATOR (REV) [READ ONLY] BIT 0-3
Default = none
0001 - Revision A
0010 - Revision B
0011 - Revision C
etc.
Function:
This read-only register indicates the revision level of the device.
76543
210
Reserved
REV3
REV2
REV1
REV0
0000
XXXX
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