4.14 Extended Audio ID Register (Index 28h) ID[1:0] Codec Configuration ID. When ID[1:0] = 00, the CS4297A is the primary audi" />
參數(shù)資料
型號: CS4299-JQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 21/52頁
文件大小: 0K
描述: IC CODEC AC 97 W/SRC 48LQFP
標(biāo)準(zhǔn)包裝: 250
系列: SoundFusion™
類型: 音頻編解碼器 '97
數(shù)據(jù)接口: 串行
分辨率(位): 18 b,20 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 87
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 管件
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
其它名稱: 598-1044
CS4299
28
4.14
Extended Audio ID Register (Index 28h)
ID[1:0]
Codec Configuration ID. When ID[1:0] = 00, the CS4297A is the primary audio codec. When
ID[1:0] = 01, 10, or 11, the CS4297A is a secondary audio codec. The state of the ID[1:0] bits
is determined at power-up from the ID[1:0]# pins.
AMAP
Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.1 compliant AC-link
slot to audio DAC mapping is supported. This bit is a shadow of the AMAP bit in the AC Mode
Control Register (Index 5Eh). The PCM playback and capture slots are mapped according to
VRA
Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is supported.
This bit always returns ‘1’, indicating that variable rate PCM audio is available.
Default
x201h. Where x is determined by the state of ID[1:0]# input pins. The Extended Audio ID Reg-
ister (Index 28h) is a read only register.
4.15
Extended Audio Status/Control Register (Index 2Ah)
VRA
Enable Variable Rate Audio. When ‘set’, the VRA bit allows access to the PCM Front DAC Rate
Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). The bit must be ‘set’ in
order to use variable PCM playback or capture rates. The VRA bit also serves as a powerdown
for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC Rate Register
(Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC
data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at
‘0’.
Default
0000h
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ID1
ID0
0
00
0
AMAP
00
VRA
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00
0
VRA
28
DS319PP6
CS4299
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