參數(shù)資料
型號(hào)： CS4124
廠商： ZF Electronics Corporation
英文描述： High Side PWM FET Controller
中文描述： 場(chǎng)效應(yīng)管高邊PWM控制器
文件頁數(shù)： 4/6頁
文件大?。?/td> 149K
代理商： CS4124
C
1198
Application Information
Oscillator
The IC sets up a constant frequency triangle wave at the
C
OSC
lead whose frequency is related to the external com-
ponents R
OSC
and C
OSC
, by the following equation:
Frequency =
The peak and valley of the triangle wave are proportional
to V
CC
by the following:
V
VALLEY
= 0.1
×
V
CC
V
PEAK
= 0.7
×
V
CC
This is required to make the voltage compensation function
properly. In order to keep the frequency of the oscillator
constant the current that charges C
OSC
must also vary with
supply. R
OSC
sets up the current which charges C
OSC
. The
voltage across R
OSC
is 50% of V
CC
and therefore:
I
ROSC
= 0.5
×
I
ROSC
is multiplied by (2) internally and transferred to the
C
OSC
lead. Therefore:
I
COSC
= ±
The period of the oscillator is:
T = 2C
OSC
×
The R
OSC
and C
OSC
components can be varied to create fre-
quencies over the range of 15Hz to 25kHz. With the sug-
gested values of 93.1k
and 470pF for R
OSC
and C
OSC
, the
nominal frequency will be approximately 20 kHz. I
ROSC
, at
V
CC
= 14V, will be 66.7 μA. I
ROSC
should not change over a
more than 2:1 ratio and therefore C
OSC
should be changed
to adjust the oscillator frequency.
Voltage Duty Cycle Conversion
The IC translates an input voltage at the CTL lead into a
duty cycle at the OUTPUT lead. The transfer function
incorporates Cherry Semiconductor’s patented Voltage
Compensation method to keep the average voltage and
current across the load constant regardless of fluctuations
in the supply voltage. The duty cycle is varied based upon
the input voltage and supply voltage by the following
equation:
Duty Cycle = 100%
×
An internal DC voltage equal to:
V
DC
= (1.683
×
V
CTL
) + V
VALLEY
is compared to the oscillator voltage to produce the com-
pensated duty cycle. The transfer is set up so that when
V
CC
= 14V the duty cycle will equal V
CTL
divided by V
REG
.
For example at V
CC
= 14V, V
REG
= 5V and V
CTL
= 2.5V, the
duty cycle would be 50% at the output. This would place a
7V average voltage across the load. If V
CC
then drops to
10V, the IC would change the duty cycle to 70% and hence
keep the average load voltage at 7V.
Figure 1: Voltage Compensation
5V Linear Regulator
There is a 5V, 5mA linear regulator available at the V
REG
lead for external use. This voltage acts as a reference for
many internal and external functions. It has a drop out of
approximately 1.5V at room temperature.
Current Sense and Timer
The IC differentially monitors the load current on a cycle
by cycle basis at the I
SENSE+
and I
SENSE-
leads. The differen-
tial voltage across these two leads is amplified internally
and compared to the voltage at the I
ADJ
lead. The gain, A
V
is set internally and externally by the following equation:
A
V
=
=
The current limit (I
LIM
) is set by the external current sense
resistor (R
SENSE
) placed across the I
SENSE+
and I
SENSE-
ter-
minals and the voltage at the I
ADJ
lead.
I
LIM
=
×
The R
CS
resistors and C
CS
components form a differential
low pass filter which filters out high frequency noise gen-
erated by the switching of the external MOSFET and the
associated lead noise. R
CS
also forms and error term in the
gain of the I
LIM
equation because the I
SENSE+
and I
SENSE-
leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50μA while
the chip is in run mode. I
ADJ
should be biased between 1V
and 4V. When the current through the external MOSFET
V
I(ADJ)
R
SENSE
1000 + R
CS
37000
37000
1000 + R
CS
V
I(ADJ)
I
SENSE+
- I
SENSE-
120%
100%
80%
60%
40%
20%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
CTL Voltage (% of V
REG
)
D
V
CC
= 8V
V
CC
= 14V
V
CC
= 16V
2.8
×
V
CTL
V
CC
V
PEAK
- V
VALLEY
I
COSC
V
CC
R
OSC
V
CC
R
OSC
0.83
R
OSC
×
C
OSC
Theory Of Operation
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