參數(shù)資料
型號: CS3843BGDR8
廠商: ZF Electronics Corporation
英文描述: ECONOLINE: RM & RL - Single Output Rail- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- High Efficiency for Low Power Applications- UL94V-0 Package Material- Toroidal Magnetics- Fully Encapsulated- Efficiency to 80%
中文描述: 離線式電流模式PWM控制電路脫線電流模式PWM控制電路
文件頁數(shù): 5/6頁
文件大小: 154K
代理商: CS3843BGDR8
Figure 3: Oscillator Timing Network and parameters
V
REF
OSC
Gnd
R
T
C
T
V
OSC
Internal Clock
LARGE R
T
(
10k
)
V
REF
Internal Clock
SMALL R
T
(
700k
)
5
C
Figure 3: Oscillator
Sawtooth Mode
Triangular Mode
V
upper
V
lower
t
c
t
d
Figure 2: Timing Diagram for key CS-384XB parameters
V
CC
I
OUT
V
OUT
Switch
Current
EA Output
V
OSC
OSC
RESET
cycle tends to exceed the maximum allowed, to prevent
transformer saturation in some power supplies, the inter-
nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
Setting the Oscillator
The oscillator timing capacitor, C
T
, is charged by V
REF
through R
T
and discharged by an internal current source
(Figure 3). During the discharge time, the internal clock
signal blanks out the output to the Low state, thus provid-
ing a user selected maximum duty cycle clamp.
Charge and discharge times are determined by the general
formulas:
(
t
c
= R
T
C
T
ln
t
d
= R
T
C
T
ln
Substituting in typical values for the parameters in the
above formulas:
V
REF
= 5.0V, V
upper
= 2.7V, V
lower
= 1.0V, I
d
= 8.3mA,
then
t
c
0.5534R
T
C
T
t
d
= R
T
C
T
ln
The frequency and maximum duty cycle can be deter-
mined from the Typical Performance Characteristics
graphs.
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to ground in a single
point ground.
The transistor and 5k
potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
)
2.3 – 0.0083 R
T
4.0 – 0.0083 R
T
(
)
V
REF
– I
d
R
T
–V
lower
V
REF
– I
d
R
T
– V
upper
(
)
V
REF
– V
lower
V
REF
– V
upper
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