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參數(shù)資料
| 型號： | CS3318-CQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANLG VOL CTRL 8CH 48-LQFP |
| 標準包裝： | 2,000 |
| 類型： | 音量控制 |
| 應(yīng)用： | 高端音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 配用： | 598-1497-ND - BOARD EVAL FOR CS3318 VOL CTRL |
4
Precision Edge
SY89827L
Micrel, Inc.
M9999-073010
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTIONS
Internal
PinNumber
PinName
I/O
Type
P/U
PinFunction
5, 6
HSTL_CLKA
Input
HSTL
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
/HSTL_CLKA
Canbeleftfloatingifnotselected.Floatinginput,ifselected
produces an indeterminate output. HSTL input signal requires
externaltermination50-to-GND.
2, 3
HSTL_CLKB
Input
HSTL
Differential clock input selected by CLK_SEL1, SEL1 and SEL2.
/HSTL_CLKB
Canbeleftfloatingifnotselected.Floatinginput,ifselected
produces an indeterminate output. HSTL input signal requires
externaltermination50-to-GND.
8,9
LVPECL_CLKA Input LVPECL
75k
DifferentialclockinputselectedbyCLK_SEL1,SEL1andSEL2.
/LVPECL_CLKA
pull-down Canbeleftfloating.Floatinginput,ifselectedproducesaLOW
at output. Requires external termination. See Figure 1.
12,13
LVPECL_CLKB Input LVPECL
75k
DifferentialclockinputselectedbyCLK_SEL2,SEL1andSEL2.
/LVPECL_CLKB
pull-down Requires external termination. See Figure 1.
7
CLK_SEL1
Input
LVTTL/
11k
SelectsHSTL_CLKAinputwhenLOWandLVPECL_CLKA
CMOS
Pull-up
input when HIGH.
14
CLK_SEL2
Input
LVTTL/
11k
SelectsHSTL_CLKBinputwhenLOWandLVPECL_CLKB
CMOS
Pull-up
input when HIGH.
16
SEL1
Input
LVTTL/
11k
SelectsinputsourceCLKAwhenLOWandCLKB
CMOS
Pull-up
when HIGH for outputs Q0 – Q9 and /Q0 – /Q9.
1
SEL2
Input
LVTTL/
11k
SelectsinputsourceCLKAwhenLOWandCLKB
CMOS
Pull-up
when HIGH for outputs Q10 – Q19 and /Q10 – /Q19.
11
OE1
Input
LVTTL/
11k
Enableinputsynchronizedinternallytopreventglitchingofthe
CMOS
Pull-up
Q0 – Q9 and /Q0 – /Q9 outputs.
15
OE2
Input
LVTTL/
11k
Enableinputsynchronizedinternallytopreventglitchingofthe
CMOS
Pull-up
Q10 – Q19 and /Q10 – /Q19 outputs.
4
VCCI
Power
Core VCC connected to 3.3V supply. Bypass with 0.1F in
parallelwith0.01FlowESRcapacitorsasclosetoVCCpinsas
possible.
17, 32, 33,
VCCO
Power
Output buffer VCC connected to 1.8V nominal supply. All VCCO
40, 41, 48, 49, 64
pins should be connected together on the PCB. Bypass with
0.1F in parallel with 0.01F low ESR capacitors as close to
VCCO pins as possible.
10
GND
Power
Ground.
63, 61, 59, 57, 55
Q0 – Q9
Output
HSTL
Differential clock outputs from CLKA when SEL1 = LOW and
53, 51, 47, 45, 43
fromCLKBwhenSEL1=HIGH.HSTLoutputs(Qand/Q)must
beterminatedwith50-to-GND.Qoutputsarestaticwhen
OE1=LOW.Unusedoutputpairsmaybeleftfloating.
62, 60, 58, 56, 54
/Q0 – /Q9
Output
HSTL
Differential clock outputs (complement) from CLKA when SEL1 =
52, 50, 46, 44, 42
LOW and from CLKB when SEL1 = HIGH. HSTL outputs (Q and
/Q)mustbeterminatedwith50-to-GND./Qoutputsarestatic
HIGH when OE1 = LOW. Unused output pairs may be left
floating.
39, 37, 35, 31, 29
Q10 – Q19
Output
HSTL
Differential outputs from CLKA when SEL2 = LOW and from
27, 25, 23, 21, 19
CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q) must be
terminatedwith50-to-GND.QoutputsarestaticLOWwhen
OE2=LOW.Unusedoutputpairsmaybeleftfloating.
38, 36, 34, 30, 28
/Q10 – /Q19
Output
HSTL
Differentialoutputs(complement)fromCLKAwhenSEL2=LOW
26, 24, 22, 20, 18
and from CLKB when SEL2 = HIGH. HSTL outputs (Q and /Q)
mustbeterminatedwith50-to-GND./QoutputsarestaticHIGH
whenOE2=LOW.Unusedoutputpairsmaybeleftfloating.
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