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參數(shù)資料
| 型號(hào)： | CS2200P-DZZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 中文描述： | PHASE LOCKED LOOP, 56 MHz, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 177K |
| 代理商： | CS2200P-DZZR |
CS2200-OTP
DS842F2
13
5.4
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to
either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is un-
locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global
parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
Figure 7. PLL Clock Output Options
Referenced Control
Parameter Definition
ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 19
ClkOutDis .............................. “M2 Configured as Output Disable” on page 15
M2Config[2:0]........................ “M2 Pin Configuration (M2Config[2:0])” on page 19
PLL Locked/Unlocked
PLL Output
2:1 Mux
M2 pin with
M2Config[1:0] = 000, 010
2:1 Mux
ClkOutUnl
0
PLL Clock Output Pin
(CLK_OUT)
0
1
0
1
PLL Clock Output
PLLClkOut
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