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參數(shù)資料
| 型號： | CS2200CP-CZZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 1/1頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN CTRL PORT 10-MSOP |
| 標準包裝： | 1 |
| 類型： | 扇出配送，分數(shù) N 合成器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 75MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | 598-1403-6 |
CS2000
Cirrus Logic, Inc. 2901 Via Fortuna Austin TX 78746 USA T 512-851-4000 T 800-888-5016 F 512-851-4977
Product Bulletin 0201-0807-PB 2007 Cirrus Logic, Inc. All rights reserved. Product information is subject to change without notice. Cirrus Logic, Cirrus, and the Cirrus Logic logo
designs are trademarks of Cirrus Logic, Inc. Other brand and product names may be trademarks or service marks of their respective owners.
CS2000 Features
High-performance analog/digital phase
locked loop
Clock multiplier/jitter reduction
Generates a low-jitter 6 – 75 MHz output
clock from a jittery or intermittent 50 Hz
to 30 MHz clock source
Clock generation/frequency synthesis
Generates a low-jitter 6 – 75 MHz clock
relative to 8 – 75 MHz reference clock
Highly accurate PLL multiplication factor
Less than 1 PPM error
Flexible control options
One-time-programmable configuration
for hardware mode
I2C / SPI control port
Configurable auxiliary output
Buffered reference clock
PLL Lock indication
Second PLL output
Buffered version of CLK_IN
Flexible sourcing of reference clock
External oscillator or clock source
Supports inexpensive local crystal
Minimal board space required
No external analog loop-filter
components required
Packaged in a 10-pin MSOP
CS2300 has internal LCO for reference clock
CS2200 is a subset and consists
of clock generation
CS2100 is a subset and consists
of clock multiplication
Featuring both a clock generator and
clock multiplier/jitter reduced clock
frequency synthesizer (clean up), Cirrus
Logic’s CS2000 is a strong entrant into
the clocking IC market. Based on a
unique hybrid analog-to-digital phase
lock loop, the CS2000 gives system
designers a unique solution for solving the
complex challenges of clock generation
and multiplication/jitter reduction.
The members of the CS2000 product
family are differentiated by the method
of control and/or a hardware mode
configuration. The CS2000-CP is
controlled via an I2C / SPI control port
and supports the full functionality of the
CS2000. The CS2000-OTP is controlled in
hardware mode via three mode pins. The
functionality of the eight selectable modes
is user defined and configured via the
one-time-programmable feature.
The CS2xxx is a growing family of
products based on the CS2000-OTP
and configured by Cirrus Logic to
support common system requirements.
Please contact Cirrus Logic for factory
configuration of the CS2000-OTP to
support your unique requirements.
3 mm
CS2000
10-pin MSOP dimensions
3 mm
CS2000
www.cirrus.com
Applications
Audio/Video Receivers
Digital Mixing Consoles
Outboard A/D and D/A converters
Digital Effects Processors
Camcorders
Satellite Radio Systems
New Clocking Family Offers System Flexibility,
Lower Cost, and Easier System Design
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS2200CP-DZZ | 功能描述:時鐘合成器/抖動清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200CP-DZZR | 功能描述:時鐘合成器/抖動清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200-OTP | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
| CS2200-OTP_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
| CS2200P-CZZ | 功能描述:時鐘合成器/抖動清除器 IC Gen Purpose PLL Clock Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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