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參數資料
| 型號： | CS2200-CP-CZZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | XO, clock |
| 英文描述： | PHASE LOCKED LOOP, 75 MHz, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件頁數： | 3/26頁 |
| 文件大小： | 307K |
| 代理商： | CS2200-CP-CZZR |
CS2200-CP
DS759PP1
11
5. APPLICATIONS
5.1
Timing Reference Clock Input
The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an
external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL out-
put the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock
directly affects the performance of the PLL and hence the quality of the PLL output.
5.1.1
Internal Timing Reference Clock Divider
The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on
the XTI/REF_CLK pin. The CS2200 supports the wider external frequency range by offering an internal
divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls
within the valid range as indicated in Figure 5.
It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent
upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Char-
acteristics” on page 7 for more details.
5.1.2
Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-
allel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 6. As shown,
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range.
Referenced Control
Register Location
RefClkDiv[1:0] ....................... “Reference Clock Input Divider (RefClkDiv[1:0])” on page 22
Figure 5. Internal Timing Reference Clock Divider
N
Internal Timing
Reference Clock
PLL Output
Fractional-N
Frequency
Synthesizer
Timing Reference
Clock Divider
÷1
÷2
÷4
XTI/REF_CLK
RefClkDiv[1:0]
8 MHz < SysClk < 18.75 MHz
8 MHz < RefClk <
Timing Reference Clock
50 MHz (XTI)
75 MHz (REF_CLK)
XTI
XTO
40 pF
Figure 6. External Component Requirements for Crystal Circuit
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CS2200CP-CZZR | 功能描述:時鐘合成器/抖動清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200CP-DZZ | 功能描述:時鐘合成器/抖動清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200CP-DZZR | 功能描述:時鐘合成器/抖動清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200-OTP | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
| CS2200-OTP_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
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