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參數(shù)資料
| 型號： | CS1088XFTR48 |
| 英文描述： | VACUUM FLUORESCENT DISPLAY DRIVER|QFP|48PIN|PLASTIC |
| 中文描述： | 真空熒光顯示驅(qū)動器| QFP封裝| 48PIN |塑料 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 136K |
| 代理商： | CS1088XFTR48 |
CS1087
http://onsemi.com
5
BLOCK DIAGRAM
AN1 – AN23: 2.0 mA
V
REG
POR
GRID1
GRID2 GRID3
AN1
AN2
AN3
AN23
AN24
AN25
AN26
AN27
AN28
AN29
V
BB
GND
GREN
STB
D
IN
CLK
D
OUT
METAL MASK ROM
Output Drive Capability
Grid Outputs: 5 mA
AN24 – AN29: 20 mA
D Q
LE
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
CLK
R
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
V
REG
V
REG
V
REG
V
REG
V
REG
V
REG
OPERATION DESCRIPTION
Upon the initial application of power, the power on reset
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the D
IN
pin at the rising
edge of the CLK input. Thirty two bits of data are capable of
being stored by the shift register. Once the desired pattern is
stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
The three GRID outputs are gated by the GREN input.
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN29 are always enabled.
The D
OUT
pin is the output of the last stage of the shift
register to allow serial cascading of this IC with other
devices. Data from the last stage of the shift register is
supplied to the D
OUT
pin delayed by 1/2 CLK cycle. Data on
the D
OUT
output changes with the falling edges of the CLK
to prevent logic race conditions between the CLK and the
D
IN
of the next IC in the serial chain.
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