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140
Output Signal Levels
All output signals are powered by the digital supply (VCC).
Table 44 summarizes the states of the output signals during
the reset state (when VCC power exists in the reset state)
and during the Power Save mode.
The RESET and NMI input pins are active during the Power
Save mode. In order to guarantee that the Power Save cur-
rent not exceed 1mA, these inputs must be driven to a volt-
age lower than 0.5V or higher than VCC-0.5V. An input
voltage between 0.5V and (VCC-0.5V) may result in power
consumption exceeding 1 mA.
Output Pins During Reset and Power-Save
t
SD
t
TT
t
PW
t
PW
t
PE
t
ED
t
PP
Row Select/
Start Charge
Pump
Select
Charge Pump/
Enable
Programming
Voltage
Programming
Pulse
Figure 76.
Flash EEPROM Memory Programming Timing
(Sample Sequence for Programming two Words into Flash EEPROM Program Memory
Table 44
Signals on a pin
Reset state
(with Vcc)
Power Save mode
Comments
PF[0:7]
PG[0:7]
PI[0:7]
PL[0:7]
PB[0:7]
PC[0:7]
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Previous state
Previous state
Previous state
Previous state
Previous state
Previous state
I/O ports will maintain their values when
entering power-save mode