- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366891 > CR16HCS5VJE8 Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | CR16HCS5VJE8 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 5/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCS5VJE8 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
5
www.national.com
3.0
Device Overview
TheCR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5
are complete microcomputers with all system timing, inter-
rupt logic, program memory, data memory, and I/O ports in-
cluded on-chip, making it well-suited to a wide range of
embedded controller applications.
3.1
The CR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5
uses a CR16B CPU core module. This is the same core used
in other CompactRISC family member designs, like DECT or
GSM chipsets.
The high performance of the CPU core results from the im-
plementation of a pipelined architecture with a two-bytes-per-
cycle pipelined system bus. As a result, the CPU can support
a peak execution rate of one instruction per clock cycle.
Compared with conventional RISC processors, the devices
differ in the following ways:
— The CPU core can use on-chip rather than external
memory. This eliminates the need for large and com-
plex bus interface units.
— Most instructions are 16 bits, so all basic instructions
are just two bytes long. Additional bytes are sometimes
required for immediate values, so instructions can be
two or four bytes long.
— Non-aligned word access is allowed. Each instruction
can operate on 8-bit or 16-bit data.
— The devices are designed to operate with a clock rate
in the 10 to 24 MHz range rather than 100 MHz or
more. Most embedded systems face EMI and noise
constraints that limit clock speed to these lower rang-
es. A lower clock speed means a simpler, less costly
silicon implementation.
— The instruction pipeline uses three stages. A smaller
pipeline eliminates the need for costly branch predic-
tion mechanisms and bypass registers, while maintain-
ing adequate performance for typical embedded
controller applications.
For more information, please refer to the CR16B Program-
mer’s Reference Manual, Literature #: 633150.
CR16B CPU CORE
3.2
The CompactRISC architecture supports a uniform linear ad-
dress space of 2 megabytes. The CR16MCS9/CR16MCS5
and CR16HCS9/CR16HCS5 implementation of this architec-
ture uses only the lowest 128K bytes of address space. Four
types of on-chip memory occupy specific intervals within this
address space:
64K bytes of flash EEPROM program memory (100K cy-
cles)
48K bytes ROM programm memory version available also
(100K cycles)
3K bytes of static RAM
2K bytes of EEPROM data memory with low endurance
(25K cycles)
128 bytes with high endurance (100K cycles)
1.5K bytes flash EEPROM memory for ISP code
MEMORY
The 3K bytes of static RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, depend-
ing on the instruction executed by the CPU. Each memory
access requires one clock cycle; no wait cycles or hold cycles
are required.
There are two types of flash EEPROM data memory storage.
The 2K bytes of EEPROM data memory with low endurance
(25K cycles) and 128 bytes of flash EEPROM data memory
with high endurance (100K cycles) are used for non-volatile
storage of data, such as configuration settings entered by the
end-user.
The 64K bytes of flash EEPROM program memory are used
to store the application program. It has security features to
prevent unintentional programming and to prevent unautho-
rized access to the program code. This memory can be pro-
grammed with a device external programming unit or with the
CR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5 in-
stalled in the application system (in-system programming).
There is a factory programmed boot memory used to store
In-System-Programming (ISP) code. (This code allows pro-
gramming of the program memory via one of the USART in-
terfaces in the final application.)
For flash EEPROM program and data memory, the
CR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5 inter-
nally generates the necessary voltages for programming. No
additional power supply is required.
3.3
The CCR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5
devices havs 56 software-configurable I/O pins, organized
into seven 8-pin ports called Port B, Port C, Port F, Port G,
Port H, Port I, and Port L. Each pin can be configured to op-
erate as a general-purpose input or general-purpose output.
In addition, many I/O pins can be configured to operate as a
designated input or output for an on-chip peripheral module
such as the USART, timer, A/D converter, or MICROWIRE/
SPI interface.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input.
INPUT/OUTPUT PORTS
3.4
The Bus Interface Unit (BIU) controls the interface between
the on-chip modules to the internal core bus. It determines
the configured parameters for bus access (such as the num-
ber of wait states for memory access) and issues the appro-
priate bus signals for each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are to be used when ac-
cessing flash EEPROM program memory, ISP memory and
the I/O area (Port B and Port C). Upon start-up the configu-
ration registers are set for slowest possible memory access.
To achieve fastest possible program execution, appropriate
values should be programmed. These settings vary with the
clock frequency and the type of on-chip device being access-
ed.
BUS INTERFACE UNIT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16HCS9VJE7Y | Microcontroller |
| CR16HCS9VJE8Y | Microcontroller |
| CR16HCT5 | |
| CR16HCT5VJE7Y | Microcontroller |
| CR16HCT5VJE8Y | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16HCS5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCS5VJI8 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJE0 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJE1 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。