FN2974.3 December 6, 2005 AC Testing Input, Output Waveform Test Load Circuits NOTES: 1. CL
參數(shù)資料
型號: CP82C84A
廠商: Intersil
文件頁數(shù): 11/11頁
文件大?。?/td> 0K
描述: IC CLK GEN 5V 25MHZ 18-DIP
標(biāo)準(zhǔn)包裝: 400
類型: 時(shí)鐘發(fā)生器,時(shí)鐘同步器,扇出配送
PLL:
輸入: TTL
輸出: TTL
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 25MHz
除法器/乘法器: 是/無
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 18-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 18-PDIP
包裝: 管件
9
FN2974.3
December 6, 2005
AC Testing Input, Output Waveform
Test Load Circuits
NOTES:
1. CL =100pF for CLK output.
2. CL = 50pF for all outputs except CLK.
3. CL = Includes probe and jig capacitance.
FIGURE 5. TEST LOAD MEASUREMENT CONDITIONS
FIGURE 6. TCHCL, TCLCH LOAD CIRCUITS
FIGURE 7. TRYLCL, TRYHCH LOAD CIRCUITS
CL
OUTPUT FROM
DEVICE UNDER TEST
(SEE NOTE 3)
R = 740
FOR ALL OUTPUTS
EXCEPT CLK
463
FOR CLK OUTPUT
2.25V
C1
C2
X1
X2
CSYNC
CLK
LOAD
(SEE NOTE 1)
F/C
EF1
CSYNC
CLK
LOAD
(SEE NOTE 1)
F/C
VCC
PULSE
GENERATOR
C1
C2
X1
X2
CLK
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
CSYNC
F/C
AEN2
PULSE
GENERATOR
TRIGGER
VCC
24MHz
READY
OSC
AEN1
RDY2
EF1
CLK
LOAD
(SEE NOTE 1)
F/C
VCC
PULSE
GENERATOR
CSYNC
RDY2
AEN2
LOAD
(SEE NOTE 2)
AEN1
READY
TRIGGER
PULSE
GENERATOR
1.5V
VOL
VIL - 0.4V
INPUT
VIH + 0.4V
OUTPUT
VOH
NOTE: Input test signals must switch between VIL (maximum) -0.4V and VIH (minimum) +0.4V. RES and F/C must switch between 0.4V
and VCC -0.4V. Input rise and fall times driven at 1ns/V. VIL ≤ VIL (max) -0.4V for CSYNC pin. VCC -4.5V and 5.5V.
82C84A
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