參數(shù)資料
型號(hào)： CP2200-GQ
廠商： Silicon Laboratories Inc
文件頁數(shù)： 67/108頁
文件大?。?/td> 0K
描述： IC ETH CTRLR SNGL-CHIP 48TQFP
標(biāo)準(zhǔn)包裝： 250
控制器類型： 以太網(wǎng)控制器，MAC/10Base-T
接口： 并行/串行
電源電壓： 3.1 V ~ 3.6 V
電流 - 電源： 75mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
配用： 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名稱： 336-1312
CP2200/1
Rev. 1.0
61
Register 34. RXCN: Receive Interface Control
Register 35. RXSTA: Receive Interface Status
Bits 7–4: UNUSED. Read = 0000b, Write = don’t care.
Bit 3:
RXINH: Receive Inhibit
Setting this bit to ‘1’ temporarily inhibits new packet reception. If a packet is currently being
received, reception will continue until the packet is received. Once set, this bit must be cleared to ‘0’
by software to resume packet reception.
Bit 2:
RXCLRV: Valid Bit Clear
Writing a ‘1’ to this bit clears the valid bit of the current packet, freeing up the buffer for new packets.
This action should only be started after all bytes of the current packet have been read (CPEND = 1).
If the packet is not completely read, RXSKIP should be used to discard the remaining bytes.
Bit 1:
RXSKIP: Skip Current Packet
Writing a ‘1’ to this bit updates discards the current packet by clearing its valid bit and advances the
AutoRead buffer pointer to the beginning of the next packet.
Bit 0:
RXCLEAR: Receive Buffer Clear
Writing a ‘1’ to this bit discards all packets in the receive buffer and resets all buffer pointers and
valid bits to zero. Note: Any packets currently in the buffer will remain in memory, however, all infor-
mation such as the starting address and length of each packet will be lost. Any new packets that
arrive will overwrite the existing data.
R/W
W
Reset Value
—
RXINH
RXCLRV
RXSKIP RXCLEAR 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x11
Bits 7–2: UNUSED. Read = 000000b, Write = don’t care.
Bit 1:
CPEND: Current Packet End Reached
This bit is automatically cleared by hardware when the valid bit for the current packet is cleared (see
RXCLRV description) or the current packet is discarded (see RXSKIP description).
0: The last byte of the current packet has not been read using the AutoRead interface.
1: The last byte of the current packet has been read using the AutoRead interface.
Bit 0:
RXBUSY: Receiving Packet
0: Receive interface is idle.
1: Receive interface is currently receiving a packet.
R/WR/WR/WR/WR/WR/W
R
Reset Value
—
CPEND
RXBUSY 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x12
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