參數(shù)資料
型號: CP2103-GMR
廠商: SILICON LABORATORIES
元件分類: 總線控制器
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, QCC28
封裝: 5 X 5 MM, LEAD FREE, QFN-28
文件頁數(shù): 16/18頁
文件大?。?/td> 394K
代理商: CP2103-GMR
CP2103
Preliminary Rev. 0.2
7
4. Pinout and Package Definitions
Table 5. CP2103 Pin Definitions
Name
Pin #
Type
Description
VDD
6
Power In
Power Out
3.0–3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output. See Section 11.
VIO
5
Power In
1.8 V to VDD I/O Supply Voltage Input.
GND
2
Ground. Must be tied to ground.
SGND
Ground. Must be tied to ground.
RST
9
D I/O
Device Reset. Open-drain output of internal POR or VDD monitor. An
external source can initiate a system reset by driving this pin low for
at least 15 s.
REGIN
7
Power In
5 V Regulator Input. This pin is the input to the on-chip voltage regu-
lator.
VBUS
8
D In
VBUS Sense Input. This pin should be connected to the VBUS sig-
nal of a USB network. A 5 V signal on this pin indicates a USB net-
work connection.
D+
3
D I/O
USB D+
D–
4
D I/O
USB D–
TXD
25
D Out
Asynchronous data output (UART Transmit)
RXD
24
D In
Asynchronous data input (UART Receive)
CTS
22*
D In
Clear To Send control input (active low)
RTS
23*
D Out
Ready to Send control output (active low)
DSR
26*
D in
Data Set Ready control input (active low)
DTR
27*
D Out
Data Terminal Ready control output (active low)
DCD
28*
D In
Data Carrier Detect control input (active low)
RI
1*
D In
Ring Indicator control input (active low)
SUSPEND
12*
D Out
This pin is driven high when the CP2103 enters the USB suspend
state.
SUSPEND
11*
D Out
This pin is driven low when the CP2103 enters the USB suspend
state.
NC
10, 13–15,
20–21
These pins should be left unconnected or tied to VDD.
GPIO.3
16
D I/O
User-configurable input or output.
GPIO.2
17
D I/O
User-configurable input or output.
GPIO.1
18
D I/O
User-configurable input or output.
GPIO.0
19
D I/O
User-configurable input or output.
*Note: Pins can be left unconnected when not used.
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